MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1135

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

19.2.2
Because the SPI is a character-oriented communication unit, the core is responsible for packing and
unpacking the receive and transmit frames. A frame consists of all of the characters transmitted or received
during a completed SPI transmission session, from the first character written to the SPITD register to the
last character transmitted following the setting of SPCOM[LST]. See
Register (SPCOM),”
The core receives data by reading the SPI receive data hold register (SPIRD). The SPI then clears the not
empty SPIE[NE] to free up the SPIRD register for the next receive operation. The core transmits data by
writing it into the SPI transmit data hold register (SPITD). The SPI then clears the not full (NF) bit in the
SPI event register (SPIE) to indicate that the SPITD register contains a character for transmission. When
the next character to be transmitted is going to be the final one in the current frame, the core sets
SPCOM[LST], and then writes the final character to SPITD.
The SPI core handshake protocol can be implemented by either using polling or interrupts.When using a
polling, the core reads the SPIE in a predefined frequency and acts according to the value of the SPIE
bits.The polling frequency depends on the SPI serial channel frequency.When using the interrupt
mechanism, setting either the not full (NF) or not empty (NE) bits of SPIE causes an interrupt to the
processor core.The core then reads SPIE and acts accordingly. The three basic modes of operation for
transmitting and receiving are master, slave and multiple-master.
The SPMODE[LEN] determines the character length sent by the hardware. The core is responsible for any
bit manipulation to pack/unpack data into the appropriate character length. See the SPMODE[LEN]
description in
19.2.3
The SPI can be programmed to work in a single- or multiple-master environment. This section describes
SPI master and slave operations in a single-master configuration. It also discusses the multiple master
environment.
The following sections summarize the main modes of operation that the SPI supports.
19.2.3.1
In master mode, the SPI sends a message to the slave peripheral, which sends back a simultaneous reply.
A single master device with multiple slaves can use general-purpose parallel I/O signals to selectively
enable slaves, as shown in
environment, the master’s SPISEL input should be forced inactive by an external pull up.
Freescale Semiconductor
SPI Transmission and Reception Process
Modes of Operation
SPI as a Master Device
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 19-4
When both NE and NF bits are set, the processor core should read the
received data before transmitting new data.
for more information.
for more information.
Figure
19-2. To eliminate the multi-master error in a single-master
NOTE
Section 19.4.1.4, “SPI Command
Serial Peripheral Interface
19-3