MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 446

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
9-52
RD_TO_PRE
FOUR_ACT
Parameter
ODT_CFG
CKE_PLS
BSTOPR
RD_EN
2T_EN
8_BE
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 9-35. Programming Differences Between Memory Types (continued)
Read to Precharge Timing
Minimum CKE Pulse Width DDR1
Four Activate Window
Registered DIMM Enable
8-beat burst enable
2T Timing Enable
ODT Configuration
Burst To Precharge Interval DDR1
Description
DDR2
DDR2
DDR2
DDR2
DDR1
DDR2
DDR2
DDR2
DDR2
DDR1
DDR1
DDR1
DDR1
DDR1
burst length is 8
the memory used (t
precharge for non-zero value of additive latency
(AL) is a minimum of AL + t
the memory used (t
the memory used (t
logical banks.
field should be set to 1
If registered DRAM modules are used, then this
field should be set to 1
be set to 1
Should be set to 0
gain extra timing margin on the interface at the
cost of address/command bandwidth.
gain extra timing margin on the interface at the
cost of address/command bandwidth.
system topology. Typically, if ODT is enabled, then
the internal IOs should be set up for termination
only during reads to DRAM.
application. Auto precharge can be enabled by
setting this field to all 0s.
application. Auto precharge can be enabled by
setting this field to all 0s.
Should be set to 010 if burst length is 4 and 100 if
Should be set according to the specifications for
Can be set to 001
Should be set according to the specifications for
Should be set to 00001
Should be set according to the specifications for
If registered DRAM modules are used, then this
If 8-beat bursts are desired, then this field should
In heavily loaded systems, this can be set to 1 to
In heavily loaded systems, this can be set to 1 to
Should be set to 00
Can be set for termination at the IOs according to
Can be set to any value, depending on the
Can be set to any value, depending on the
Differences
RTP
CKE
FAW
). Time between read and
)
). Only applies to eight
RTP
cycles.
Freescale Semiconductor
Section/Page
9.4.1.12/9-26
9.4.1.6/9-16
9.4.1.6/9-16
9.4.1.6/9-16
9.4.1.7/9-18
9.4.1.7/9-18
9.4.1.7/9-18
9.4.1.8/9-21