MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 527

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.4.4.4.1
The RAM word is a 32-bit microinstruction stored in one of 64 locations in the RAM array. It specifies
timing for external signals controlled by the UPM.
LCRR[CLKDIV] = 4 or 8, the CST
LBS[0:1] at each quarter phase of the bus clock. When LCRR[CLKDIV] = 2, CST2 and CST4 are ignored
and the external has the values defined by CST1 and CST3 but extended to half the clock cycle in duration.
The same interpretation occurs for the BST
Table 10-40
Freescale Semiconductor
Reset
Reset
W
W
R
R
Bits
0
1
2
3
4
5
6
7
CST1 CST2 CST3 CST4 BST1 BST2 BST3 BST4
G3T1 G3T3
16
0
contains descriptions of the RAM word fields.
Name
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
CST1
CST2
CST3
CST4
BST1
BST2
BST3
BST4
17
RAM Words
1
G4T1/
DLT3
18
2
LCRR[CLKDIV] = 4 or 8. Defines the state (0 or 1) of LCS n during bus clock half phase 1 if
LCRR[CLKDIV] = 2.
LCRR[CLKDIV] = 4 or 8. Ignored when LCRR[CLKDIV] = 2.
LCRR[CLKDIV] = 4 or 8. Defines the state (0 or 1) of LCS n during bus clock half phase 2 if
LCRR[CLKDIV] = 2.
LCRR[CLKDIV] = 4 or 8. Ignored when LCRR[CLKDIV] = 2.
(LCRR[CLKDIV] = 4 or 8) or bus clock half phase 1 (LCRR[CLKDIV] = 2), in conjunction with
BR n [PS] and LA[24:25].
(LCRR[CLKDIV] = 4 or 8), in conjunction with BR n [PS] and LA[24:25]. Ignored when
LCRR[CLKDIV] = 2.
(LCRR[CLKDIV] = 4 or 8) or bus clock half phase 2 (LCRR[CLKDIV] = 2), in conjunction with
BR n [PS] and LA[24:25].
(LCRR[CLKDIV] = 4 or 8), in conjunction with BR n [PS] and LA[24:25]. Ignored when
LCRR[CLKDIV] = 2.
Chip select timing 1. Defines the state (0 or 1) of LCS n during bus clock quarter phase 1 if
Chip select timing 2. Defines the state (0 or 1) of LCS n during bus clock quarter phase 2 if
Chip select timing 3. Defines the state (0 or 1) of LCS n during bus clock quarter phase 3 if
Chip select timing 4. Defines the state (0 or 1) of LCS n during bus clock quarter phase 4 if
Byte select timing1. Defines the state (0 or 1) of LBS during bus clock quarter phase 1
Byte select timing 2. Defines the state (0 or 1) of LBS during bus clock quarter phase 2
Byte select timing 3. Defines the state (0 or 1) of LBS during bus clock quarter phase 3
Byte select timing 4. Defines the state (0 or 1) of LBS during bus clock quarter phase 4
WAEN
G4T3/
19
3
G5T1 G5T3
Table 10-40. RAM Word Field Descriptions
20
4
n
Figure 10-64. RAM Word Fields
and BST
21
5
n
bits when LCRR[CLKDIV] = 2.
22
6
n
REDO
bits determine the state of UPM signals LCSn and
23
Figure 10-37
7
All zeros
All zeros
LOOP EXEN
Description
24
8
G0L
25
9
shows the RAM word fields. When
10
26
AMX
G0H
11
27
G1T1
NA
12
28
Enhanced Local Bus Controller
G1T3
UTA
13
29
TODT LAST
G2T1
14
30
G2T3
10-79
15
31