MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 263

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

5.7.5.1
The global timers configuration registers (GTCFR1 and GTCFR2), shown in
contain configuration parameters used by the timers. These registers allow simultaneous starting, stopping
and resetting of a pair of timers (1 and 2 or 3 and 4) or of a groups of timers (1, 2, 3, and 4) if one bus cycle
is used. GTCFR is cleared by reset.
Table 5-57
Freescale Semiconductor
Offset 0x00
Reset
Bits
0
1
2
3
W
R
Name
PCAS
RST2
STP2
BCM
PCAS
defines the bit fields of GTCFR1.
0
Global Timers Configuration Registers (GTCFR n )
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
For proper operation of the timers, do not change the modes of operation and
enable the timer in the same register write operation. The modes can be
changed when GTCFRn[RSTn] is cleared. However, when GTCFRn[RSTn]
are set, they are the only bits that can be changed.
Pair-cascade mode
0 Normal operation
1 Timers 1 and 2 cascade to form a 32-bit timer.
Note: This bit is ignored in super-cascade mode (GTCFR2[SCAS] = 1).
Note: It is allowed to change the value of this bit only when the corresponding timers are in reset mode.
Backward compatible mode
0 Provide backward compatibility to PowerQUICC II family timers. In this mode GTCFR1[GM2] bit will
1 Normal operational mode
Stop timer 2
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 2, except the
Reset timer 2
0 Reset the timer 2, including GTMDR2, GTRFR2, GTCNR2, GTCPR2, and GTEVR2 (a software reset is
1 Enable the corresponding timer if the STP2 bit is cleared.
control the gate mode for timers 1 and 2 and GTCFR2[GM4] bit will control the gate mode for timers 3
and 4. GTCFR1[GM1] and GTCFR2[GM3] bits are ignored.
Register Interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
identical to an external reset).
Figure 5-40. Global Timers Configuration Register 1 (GTCFR1)
Thus, the user should first clear the RST1 and RST2 bits (without changing PCAS) and then, in a
separate write to the register, change the value of PCAS.
BCM
1
STP2
Table 5-57. GTCFR1 Bit Settings
2
RST2
3
NOTE
All zeros
Description
GM2
4
GM1
5
Figure 5-40
STP1
6
Access: Read/Write
System Configuration
and
Figure
RST1
7
5-41,
5-55