MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 168

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Reset, Clocking, and Initialization
4-2
CFG_CLKIN_DIV
CFG_RESET_
SOURCE[0:3]
SRESET
Signal
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I/O
I
I
I
The SRESET input is connected directly to the soft reset input of the e300c3 core. The assertion of
the e300 soft reset input, SRESET, causes a high priority interrupt to the e300 core as described in
Section 4.2.1, “Reset Operations.”
MPC8313E. The SRESET input is not registered in the reset status register (RSR).
Reset configuration word source selection. These signals are on device pins that have other functions
when the device is not in reset. They are sampled during the assertion of PORESET to determine the
interface from which the device loads the reset configuration words.
Clock in division selection. This signal is located on a device pin that has another function when the
device is not in reset state. This signal is sampled during the assertion of PORESET to determine
whether SYS_CLK_IN is divided by two.
State Meaning Asserted—Indicates that the processor must initiate a system reset interrupt.
State Meaning See
State Meaning See
Requirements An open-drain signal. An external pull-up is required.
Requirements During PORESET and HRESET flows, all other signal drivers connected to these
Requirements During PORESET and HRESET flows, all other signal drivers connected to this
Reset State Always input
Reset State Input during power-on and hard reset flows. Functional signal after reset flow
Reset State Always input
Timing Assertion—Occurs at any time, asynchronously to any clock.
Timing These signals are sampled during the assertion of PORESET after a stable clock is
Timing This signal is sampled during the assertion of PORESET after a stable clock is
Table 4-1. System Control Signals (continued)
Negated—Indicates that the interrupt is not being requested.
Negation—Occurs after being serviced. (PCI host mode) or PCI_CLK (PCI agent
supplied (PORESET flow) and must be pulled high or low by external resistors as
long as HRESET is asserted.
signals must be in the high-impedance state. Refer to the hardware specifications
for proper resistor values to pull reset configuration signals high or low.
completes.
supplied (PORESET flow), and it must be pulled high or low by external resistors as
long as HRESET is asserted.
signal must be in the high-impedance state. Refer to the hardware specifications for
proper resistors values to pull reset configuration signals high or low.
Section 4.3.1.1, “Reset Configuration Word
Section 4.3.1.2, “SYS_CLK_IN Division.”
mode)
It does not reset the e300 core or any other portion of the
Description
Source.”
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