MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 834

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
Table 15-114
15.5.3.10.6 Timer Status Register (TMR_STAT)
This register requires the eTSEC filer to be enabled (via RCTRL[FILREN]). When eTSEC generates an
interrupt based on the timestamp event for a received packet, the queue ID which the incoming packet will
be sent to is captured in this register. This register update is synchronized with the RXF interrupt of the
corresponding received packet. Writing 1 to any bit of this register clears it.
definition for the TMR_STAT register.
15-116
Offset eTSEC1:0x2_4E10
Reset
Reset
24–30
0–21
Bits
22
23
31
W
W
R
R
Offset eTSEC1:0x2_4E14
Reset
W
R
16
0
TXP2EN
TXP1EN
0
RXPEN
Name
describes the fields of the TMR_PEMASK register fields for the timer.
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Transmit PTP packet event 2 enable
Transmit PTP packet event 1 enable
Reserved
Receive PTP packet event enable
—
Table 15-114. TMR_PEMASK Register Field Descriptions
Figure 15-108. TMR_PEMASK Register Definition
Table 15-115. TMR_STAT Register Definition
21
TXP2EN TXP1EN
—
22
All zeros
All zeros
All zeros
—
23
Description
24
Figure 15-115
—
25 26
Freescale Semiconductor
STAT_VEC
Access: Read/Write
Access: Mixed
describes the
30
RXPEN
31
15
31