MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 884

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
For stack L2 (that is, more than one ethertypes) header, the Ethernet parser traverses through the header
until it finds the last valid ethertype or the ethertype is unsupported. Below is a description of what the
Ethernet header parser recognizes for stack L2 header.
The L3 parser is enabled by RCTRL[PRSDEP] = 10 or 11. It begins when the Ethernet parser ends and a
valid IPv4/v6 ethertype is found. The L4 header is enabled by RCTRL[PRSDEP] = 11. It begins when the
L3 parser ends and a valid TCP/UDP next protocol is found and no fragment frame is found. The primary
functionalities of L3(IPv4/6) and L4(TCP/UDP) parsers are as follows:
15-166
Note: * means that it is the next protocol
Row—Next Supported L2
Column—Current L2
•
•
•
•
JUMBO/SNAP
— JUMBO and SNAP header
— IPV4
— IPV6
— VLAN
— MPLSU/MPLSM
— PPPOES
— ARP
IP recognition (v4/v6, ARP, encapsulated protocol)
IP header checksum verification
IPv4/6 over IPv4/6 (tunneling)—parse headers and find layer 4 protocol
IP layer 4 protocol/next header extraction
LLC/SNAP
Ethertype
Ethertype
MPLSM
MPLSU
PPOES
VLAN
IPV4
IPV6
ARP
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
SNAP
Table 15-154. Supported Stack L2 Ethernet Headers
LLC/
N
N
N
N
Y
N
N
N
N
JUMBO/
SNAP
N
N
N
N
N
N
N
N
Y
IPV4
Y*
Y*
Y
Y
N
N
Y
Y
N
IPV6
Y*
Y*
Y
Y
N
N
Y
Y
N
VLAN
N
N
N
N
N
N
Y
Y
Y
MPLSU
N
N
N
Y
Y
Y
Y
Y
y
MPLSM
Y
Y
N
N
Y
Y
Y
Y
N
Freescale Semiconductor
PPOES
Y
Y
N
N
Y
N
N
N
N
ARP
N
N
N
N
N
N
Y
Y
Y