MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 771

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5.3.3.4
The RQUEUE register enables each of the RxBD rings 0–7. By default, RxBD ring 0 is enabled.
Figure 15-25
Table 15-30
Freescale Semiconductor
11–15
16–31
Offset eTSEC1:0x2_4314; eTSEC2:0x2_5314
Reset
3–10
0–23
\
Bits
Bits
24
25
26
27
28
W
R
0
0 0 0 0 0 0 0 0
Name
Name
ICFT
ICTT
EN0
EN1
EN2
EN3
EN4
—
—
describes the RQUEUE register.
describes the definition for the RQUEUE register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Receive Queue Control Register (RQUEUE)
Interrupt coalescing frame count threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines how many frames are received before raising an interrupt. The eTSEC threshold counter is reset
to ICFT following an interrupt. The value of ICFT must be greater than zero avoid unpredictable behavior.
Reserved
Interrupt coalescing timer threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines the maximum amount of time after receiving a frame before raising an interrupt. If frames have
been received but the frame count threshold has not been met, an interrupt is raised when the threshold timer
reaches zero. The threshold timer is reset to the value in this field and begins counting down upon receiving
the first frame having its RxBD[I] bit set. The threshold value is represented in units equal to 64 periods of the
clock specified by RXIC[ICCS]. ICTT must be greater than zero to avoid unpredictable behavior.
Reserved
Receive queue 0 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 1 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 2 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 3 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 4 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
1
0
Table 15-29. RXIC Field Descriptions (continued)
0
Figure 15-25. RQUEUE Register Definition
Table 15-30. RQUEUE Field Descriptions
0
—
0
0
0
0
Description
Description
0 0 0 0 0 0 0 0
23
Enhanced Three-Speed Ethernet Controllers
EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7
24
1
25
0
26
0
27
0
Access: Read/Write
28
0
29
0
30
0
15-53
31
0