MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1144

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset 0x024
Reset
Serial Peripheral Interface
Table 19-5
19.4.1.3
The SPI mask register (SPIM), shown in
recognized by the SPI. When an event is recognized, the SPI sets the corresponding SPIE bit. Setting a
19-12
0–16
17
18
19
20
24–31 —
Bits
21
22
23
W
R
0
—
LT
DNR
OV
UN
MME
Name
NE
NF
describes the SPIE fields.
SPI Mask Register (SPIM)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, should be cleared.
Last character was transmitted.
The last character is transmitted and new data can be written to SPID for further transmission.
Note: Data not ready. In slave mode only when SPISEL is asserted before data is ready in the SPI, IDLE is
Slave/master overrun.
Indicates whether an overrun has occurred during reception.
In case of overrun the SPI continues transmission/reception process while reporting overrun for the missing
characters.
Slave underrun. Indicates whether the SPI transmitter did not have data to transmit on time, and therefore,
whether IDLE was sent on the line. Valid only in slave mode (SPMODE[M/S]) = 0.
In master mode (SPMODE[M/S]) = 1) if the SPI’s transmitter has no valid data to transmit the SPICLK stop
toggling and transmission/reception is frozen (no underrun is reported), when data is written to the SPITD the
transmission resumes.
Multiple-master error. Set when SPISEL is asserted externally while the SPI is in master mode. Note that the
MME error can occur in loopback mode.
Not empty. When set Indicates that SPIRD contains a received character.
0 The receiver is empty
1 The receiver has valid received data and indications about LST (command register) and OV (SPIE).The
Not full. Indicates whether SPITD is not in use and a new character can be written to it by the core.
0 The transmitter is full.
1 The transmitter is not full. The core is free to write to the transmitter. NF must be clear to enable the
Reserved. Should be cleared.
core is free to read the content of the receiver. Reading the receiver SPIRD clears NE if no more data is
available.
transmission of another character (writing to the transmitter clears NF)
sent on the line and UN bit is also asserted the SPI should be disable to restart its operation.
—
Figure 19-7. SPIE—SPI Event Register Definition
Table 19-5. SPIE Field Descriptions
Figure
19-8, enables/masks interrupts for events that are
16
All zeros
w1c w1c w1c w1c w1c
LT DNR OV UN MME NE NF
17
Description
18
19
20
21
22
23
24
Freescale Semiconductor
Access: Mixed
—
31