MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 254

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
Table 5-49
5.6.5.2
The periodic interval timer load register (PTLDR), shown in
loaded in a 32-bit PIT counter.
Table 5-50
5-46
26–30
0–23
0–31
Offset 0x04
Reset
Bits
Bits
24
25
31
W
R
0
Name
CLDV
Name
CLEN
CLIN
PIM
—
—
defines the bit fields of PTCNR.
defines the bit fields of PTLDR.
Periodic Interval Timer Load Register (PTLDR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Contains the 32-bit value to be loaded in a 32-bit PIT counter.
Write reserved, read = 0
Clock enable control bit. Controls the counting of the PIT. When the PIT’s clock is disabled, the counter
maintains its old value. When the counter’s clock is enabled, it continues counting using the previous value.
0 Disable counter.
1 Enable counter.
Input clock control bit. The input clock to the PIT can be either an internal system clock or an external PIT
clock.
0 The input clock to the periodic interrupt timer is internal system clock.
1 The input clock to the periodic interrupt timer is external PIT clock.
Write reserved, read = 0
Periodic interrupt mask bit. Used to enable or disable (mask) the PIT periodic interrupt.
0 Periodic interrupt generation disabled.
1 Periodic interrupt generation enabled.
Figure 5-34. Periodic Interval Timer Load Register (PTLDR)
Table 5-49. PTCNR Bit Settings
Table 5-50. PTLDR Bit Settings
All zeros
CLDV
Description
Description
Figure
5-34, contains the 32-bit value to be
Freescale Semiconductor
Access: Read/Write
31