MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 467

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.3.1.3
Figure 10-6
Table 10-10
Freescale Semiconductor
20–22
24–28
Offset 0x0_5068
Bits
Reset
0–31
Bits
19
23
29
30
31
W
R
BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
0
Name
EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
TRLX
Name
EAD
—
—
BI
A
shows the fields of the UPM memory address register (MAR).
describes the MAR fields.
UPM Memory Address Register (MAR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
Reserved
Burst inhibit. Indicates if this memory bank supports burst accesses.
0 The bank supports burst accesses.
1 The bank does not support burst accesses. The selected UPM executes burst accesses as a series of
Reserved
Timing relaxed. Works in conjunction with EHTR to extend hold time on read accesses.
access from the current bank and the next access.
External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).
0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)
1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by
Address that can be output to the address signals under control of the AMX bits in the UPM RAM word.
single accesses.
LCRR[EADC]).
TRLX EHTR
0
0
1
1
Table 10-9. OR
0
1
0
1
Figure 10-6. UPM Memory Address Register (MAR)
The memory controller generates normal timing. No additional cycles are inserted.
1 idle clock cycle is inserted.
4 idle clock cycles are inserted.
8 idle clock cycles are inserted.
Table 10-10. MAR Field Descriptions
n
—
UPM Field Descriptions (continued)
All zeros
Description
Description
A
Meaning
Enhanced Local Bus Controller
Access: Read/Write
10-19
31