MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 538

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.5.1.5
In case a system contains a memory hierarchy with high speed synchronous memories (synchronous
SRAM) and lower speed asynchronous memories (for example, FLASH EPROM and peripherals) the
GPCM-controlled memories should be decoupled by buffers to reduce capacitive loading on the bus.
Those buffers have to be taken into account for the timing calculations.
To calculate address setup timing for a slower peripheral/memory device, several parameters have to be
added: propagation delay for the address latch, propagation delay for the buffer and the address setup for
the actual peripheral. Typical values for the two propagation delays are in the order of 3–6 ns, so for a
133-MHz bus frequency, LCS should arrive on the order of 3 bus clocks later.
For data timings, only the propagation delay of one buffer plus the actual data setup time has to be
considered.
10-90
Local Bus Interface
GPCM Timings
Local Bus Interface
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 10-71. Local Bus Peripheral Hierarchy for High Bus Speeds
LBCTL
LAD[0:15]
LAD n
LALE
LBCTL
LA n
LALE
Figure 10-72. GPCM Address Timings
Muxed Address/Data
Unmuxed Address
Buffered Data
Latch
A/D
LE
DIR
Latch
A
Q
B
Buffer
Muxed Address/Data
Unmuxed Address
Buffered Address
A
DQ
MA
A
Peripherals
Device
Memories
Input
Pin
Slower
and
A
DQ
Peripherals
SSRAM
Memories
Slower
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