MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1030

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16-102
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Transaction Error (XactErr). Timeout, data CRC failure, etc. The Cerr field is decremented and the
XactErr bit in the Status field is set. The complete split transaction is immediately retried (if Cerr
is non-zero).If there is not enough time in the micro-frame to complete the retry and the endpoint
is an IN, or Cerr is decremented to a zero from a one, the queue is halted. If there is not enough
time in the micro-frame to complete the retry and the endpoint is an OUT and Cerr is not zero, then
this state is exited (that is, return to Do Start Split). This results in a retry of the entire OUT split
transaction, at the next poll period. Refer to Chapter 11 Hubs (specifically the section on full- and
low-speed interrupts) in the USB Specification Revision 2.0 for detailed requirements on why these
errors must be immediately retried.
ACK. This can only occur if the target endpoint is an OUT. The target endpoint ACK'd the data
and this response is a propagation of the endpoint ACK up to the host controller. The host controller
must advance the state of the transfer. The Current Offset field is incremented by Maximum Packet
Length or Bytes to Transfer, whichever is less. The field Bytes To Transfer is decremented by the
same amount. And the data toggle bit (dt) is toggled. The host controller will then exit this state for
this queue head. The host controller must reload Cerr with maximum value on this response.
Advancing the transfer state may cause other process events such as retirement of the qTD and
advancement of the queue.
MDATA. This response will only occur for an IN endpoint. The transaction translator responded
with zero or more bytes of data and an MDATA PID. The incremental number of bytes received is
accumulated in QH[S-bytes]. The host controller must not adjust Cerr on this response.
DATA0/1. This response may only occur for an IN endpoint. The number of bytes received is
added to the accumulated byte count in QH[S-bytes]. The state of the transfer is advanced by the
result and the host controller exits this state for this queue head.
Advancing the transfer state may cause other processing events such as retirement of the qTD and
advancement of the queue.
If the data sequence PID does not match the expected, the entirety of the data received in this split
transaction is ignored, the transfer state is not advanced and this state is exited.
NAK. The target endpoint Nak'd the full- or low-speed transaction. The state of the transfer is not
advanced, and this state is exited. The host controller must reload Cerr with maximum value on
this response.
ERR. There was an error during the full- or low-speed transaction. The ERR status bit is set, Cerr
is decremented, the state of the transfer is not advanced, and this state is exited.
STALL. The queue is halted (an exit condition of the Execute Transaction state). The status field
bits: Active bit is cleared and the Halted bit is set and the qTD is retired. Responses which are not
enumerated in the list or which are received out of sequence are illegal and may result in undefined
host controller behavior. The other possible combinations of tests A, B, C, and D may indicate that
data or response was lost.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 16-68
lists the possible combinations and the appropriate action.
Freescale Semiconductor