MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 442

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
9.5.9
Transfers to and from memory are always performed in four- or eight-beat bursts. For transfer sizes other
than four or eight beats, the data transfers are still operated as four- or eight-beat bursts. The DDR memory
controller uses data masks to prevent all unintended full double words from writing to SDRAM. For
example, if a write transaction is desired with a size of one double word (8 bytes), then the second, third,
and fourth beats of data are not written to DRAM.
Table 9-33
the possible transfer sizes with each of the possible starting double-word offsets. All underlined
double-word offsets are valid for the transaction.
9.5.10
The DDR memory controller supports an open/closed page mode with an allowable open page for each
logical bank of DRAM used. In closed page mode for DDR SDRAMs, the DDR memory controller uses
the SDRAM auto-precharge feature, which allows the controller to indicate that the page must be
automatically closed by the DDR SDRAM after the READ or WRITE access. This is performed using
MA[10] of the address during the COMMAND phase of the access to enable auto-precharge.
Auto-precharge is non-persistent in that it is either enabled or disabled for each individual READ or
WRITE command. It can, however, be enabled or disabled separately for each chip select.
When the DDR memory controller operates in open page mode, it retains the currently active SDRAM
page by not issuing a precharge command. The page remains opens until one of the following conditions
occurs:
Page mode can dramatically reduce access latencies for page hits. Depending on the memory system
design and timing parameters, using page mode can save two to three clock cycles for subsequent burst
accesses that hit in an active page. Also, better performance can be obtained using more banks, especially
in systems which use many different channels. Page mode is disabled by clearing
DDR_SDRAM_INTERVAL[BSTOPRE] or setting CSn_CONFIG[AP_nEN].
9-48
•
•
•
Refresh interval is met.
The user-programmable DDR_SDRAM_INTERVAL[BSTOPRE] value is exceeded.
There is a logical bank row collision with another transaction that must be issued.
lists the data beat sequencing to and from the DDR SDRAM and the data queues for each of
DDR Data Beat Ordering
Page Mode and Logical Bank Retention
1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
All underlined double-word offsets are valid for the transaction.
2 double words
3 double words
1 double word
Transfer Size
Table 9-33. Memory Controller–Data Beat Ordering
Starting Double-Word Offset
0
1
2
3
0
1
2
0
1
Double-Word Sequence
DRAM and Queues
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
3 - 0 - 1 - 2
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
0 - 1 - 2 - 3
1 - 2 - 3 - 0
1
to/from
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