MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 528

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10-80
10–11
Bits
8–9
12
13
14
15
16
17
18
19
20
21
G4T3/WAEN General purpose line 4 timing 3/wait enable. Bit function is determined by M x MR[GPL4].
G4T1/DLT3 General purpose line 4 timing 1/delay time 3. The function of this bit is determined by
Name
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
G1T1
G1T3
G2T1
G2T3
G3T1
G3T3
G5T1
G5T3
G0H
G0L
General purpose line 0 lower. Defines the state of LGPL0 during the bus clock quarter phases
1 and 2 (first half phase).
00 Value defined by M x MR[G0CL]
01 Reserved
10 0
11 1
General purpose line 0 higher. Defines the state of LGPL0 during the bus clock quarter phases
3 and 4 (second half phase).
00 Value defined by M x MR[G0CL]
01 Reserved
10 0
11 1
phases 1 and 2 (first half phase).
phases 3 and 4 (second half phase)
General purpose line 2 timing 1. Defines state (0 or 1) of LGPL2 during bus clock quarter
phases 1 and 2 (first half phase).
phases 3 and 4 (second half phase).
phases 1 and 2 (first half phase).
phases 3 and 4 (second half phase).
M x MR[GPL4].
If M x MR[GPL4] = 0 and LGPL4/LUPWAIT pin functions as an output (LGPL4), G4T1/DLT3
defines the state (0 or 1) of LGPL4 during bus clock quarter phases 1 and 2 (first half phase).
If M x MR[GPL4] = 1 and LGPL4/LUPWAIT functions as an input (LUPWAIT), if a read burst or
single read is executed, G4T1/DLT3 defines the sampling of the data bus as follows:
0 In the current word, the data bus should be sampled at the start of bus clock quarter phase
1 In the current word, the data bus should be sampled at the start of bus clock quarter phase
If M x MR[GPL4] = 0 and LGPL4/LUPWAIT pin functions as an output (LGPL4), G4T3/WAEN
defines the state (0 or 1) of LGPL4 during bus clock quarter phases 3 and 4 (second half phase).
If M x MR[GPL4] = 1 and LGPL4/LUPWAIT functions as an input (LUPWAIT), G4T3/WAEN is
used to enable the wait mechanism:
0 LUPWAIT detection is disabled.
1 LUPWAIT is enabled. If LUPWAIT is detected as being asserted, a freeze in the external
phases 1 and 2 (first half phase).
phases 3 and 4 (second half phase).
General purpose line 1 timing 1. Defines the state (0 or 1) of LGPL1 during bus clock quarter
General purpose line 1 timing 3. Defines the state (0 or 1) of LGPL1 during bus clock quarter
General purpose line 2 timing 3. Defines the state (0 or 1) of LGPL2 during bus clock quarter
General purpose line 3 timing 1. Defines the state (0 or 1) of LGPL3 during bus clock quarter
General purpose line 3 timing 3. Defines the state (0 or 1) of LGPL3 during bus clock quarter
General purpose line 5 timing 1. Defines the state (0 or 1) of LGPL5 during bus clock quarter
General purpose line 5 timing 3. Defines the state (0 or 1) of LGPL5 during bus clock quarter
1 of the next bus clock cycle.
3 of the current bus clock cycle.
signals logical values occurs until LUPWAIT is detected as being negated.
Table 10-40. RAM Word Field Descriptions (continued)
Description
Freescale Semiconductor