MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1164

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Revision History
6.2.1, 6-2
8.4.2, 8-6
9.4.1.2, 9-10
9.5.5.1, 9-34
9.6.1, 9-50
Chapter 10
10.1.3, 10-3
10.2, 10-4
A-6
2 Gbits
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
In Table 6-2, reserved fields changed from “Write reserved, read = 0” to
“Reserved, write should preserve reset value.”
In table 8-2, signal IRQ[0:40:7], in the Description column (State Meaning),
changed the first sentence to read:
When an external interrupt request signal is asserted, the priority is checked by the
IPIC unit, and the interrupt is conditionally passed to the processor.
In Table 9-7, Bits 9–11 row, changed 011–111 Reserved to 011 Reserved.
In Table 9-7, Bits 13–15 row, changed 011–111 Reserved to 011 Reserved.
In Table 9-26, added the following row:
Changed ‘Row x Column x Sub-Bank Bits’ column for the 1 Gbits, 2 Gbits, and
4 Gbits rows to: ... x 2.
In Table 9-35, for ODT_PD_EXIT, changed it to be set to 0001 for DDR1; for
FOUR_ACT, changed it to be set for 00001 for DDR1.
Reformatted registers throughout Chapter 10, “Enhanced Local Bus Controller.”
Modified frequencies 333 and 666 MHz to 33.3 and 66.6 MHz, respectively.
Added eLBC IP Rev. 1.1 features.
Removed references to PLL.
In the first paragraph, second sentence replace with the following:
The internal transaction address is limited to 32 bits, so all chip selects must fall
within the 4-Gbyte window addressed by the internal transaction address. When a
memory transaction is dispatched to the eLBC, the internal transaction address is
compared with the address information of each bank (chip select).
In the first paragraph, last sentence, replaced with the following:
Thus, with the eLBC in GPCM or FCM, or UPM mode, only one of the four chip
selects is active at any time for the duration of the transaction except in the case
of UPM refresh where all UPM machines that are enabled for refresh have
concurrent chip select assertion.
In Table 10-2, LGPL0/LFCLE row, changed the first sentence in the State
Meaning to read:
Asserted/Negated—In UPM mode, LGPL0 is one of six general purpose signals;
it is driven with a value programmed into the UPM array.
In the LGPL1/LFALE row, changed the first sentence in the State Meaning to
read:
Asserted/Negated—In UPM mode, LGPL1 is one of six general purpose signals;
it is driven with a value programmed into the UPM array.
In the LOE/LGPL2/LFRE row, changed the second and third sentences in the
State Meaning to read:
256Mbits x 8
15 x 10 x 2
1 Gbytes
Freescale Semiconductor
2 Gbytes