MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1183

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

5.4.3, 5-28
5.4.4, 5-29
5.7.1, 5-48
5.8.4.7.2, 5-84
7.3.1, 7-15
7.3.4.2, 7-31
9.4.1.6, 9-17
9.4.1.6, 9-17
9.4.1.6, 9-17
9.5, 9-33
9.5.1.1, 9-34
9.5.1.1, 9-35
9.5.1.1, 9-35
10.1.2, 10-2
10.2, 10-4
10.2, 10-5
10.2, 10-10
10.3.1.1, 10-11
10.3.1.2.2, 10-13
10.3.1.2.3, 10-16
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Under the bullet, ‘WDT reset/interrupt output mode,’ replaced ‘soft reset’ with
‘hard reset.’
In Table 5-32, changed the reset value of SWSRR to 0x0000, as it is a 16-bit
register.
Throughout this section, removed references to internal clock signal ipg_clock.
Modified item 8, by adding ‘PMC interrupt clearing sequence.’
In Figure 7-2, removed Performance Monitor section (it is not available for the
e300c2 and earlier core).
Table 7-7, under System Reset, the description should read:
Caused by the asserton of hreset
In Table 9-11, for CPO, changed 11111 to Reserved, and removed Automatic
calibration.
Fixed spacing on bit settings of FOUR_ACT.
Removed text from description of TIMING_CFG_2[FOUR_ACT]: ‘This field is
concatenated with TIMING_CFG_3[EXT_FOUR_ACT] to obtain a 5-bit value
for the total activate to precharge time. Note that the decode of 000000-000011 is
equal to 16-19 clocks when TIMING_CFG_3[EXT_ACTTOPRE] = 0, but it is
equal to 03 clocks when TIMING_CFG_3[EXT_ACTTOPRE] = 1.’
Modified Figure 9-22 to correctly represent the DDR SDRAM configuration.
Fixed cross-references to the DDR SDRAM tables.
In Tables 9-25 and 9-26, fixed the row for 2-Gbit and 4-Gbit memory
configurations.
In Table 9-26, added a new memory configuration for the 4-Gbits row as follows:
4 Gbits | 512 Mbits × 8 | 15 × 11 × 3 | 2 Gbytes | 4 Gbytes
Modified the feature list by removing the, ‘Up to 256-byte bursts, arbitrarily
aligned,’ statement.
In Table 10-1, for signal LAD, changed the number of signals from 32 to 16.
In Table 10-2, removed text from the LALE state meaning description.
In Table 10-3, changed footnote to read:
FMR[BOOT] is set during reset if RCWH[RLEXT] selects FCM as the boot
controller.
In Figure 10-2, modified the first sentence of the footnote to read:
BR0 has its valid bit (V) set for RCWH[ROMLOC] = LBC.
Added a new table, Table 10-6. Reset Value of OR0 Register, and renumbered the
remaining tables.
In Figure 10-3, filled in value for TBD, ‘bit P is configured from the value of
RCWH[ROMLOC].’ Removed field SSS from reset and replaced it with 010 and
reference in footnote.
Revision History
A-25