MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1003

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.6.7
The periodic schedule traversal is enabled or disabled through USBCMD[PSE] (periodic schedule enable).
If USBCMD[PSE] is cleared, then the host controller simply does not try to access the periodic frame list
via the PERIODICLISTBASE register. Likewise, when USBCMD[PSE] is a one, then the host controller
does use the PERIODICLISTBASE register to traverse the periodic schedule. The host controller will not
react to modifications to USBCMD[PSE] immediately. In order to eliminate conflicts with split
transactions, the host controller evaluates USBCMD[PSE] only when FRINDEX[2–0] is zero. System
software must not disable the periodic schedule if the schedule contains an active split transaction work
item that spans the 0b000 micro-frame. These work items must be removed from the schedule before
USBCMD[PSE] is cleared. USBSTS[PS] (periodic schedule status) indicates status of the periodic
schedule. System software enables (or disables) the periodic schedule by setting (or clearing)
USBCMD[PSE]. Software then can poll USBSTS[PS] to determine when the periodic schedule has made
the desired transition. Software must not modify USBCMD[PSE] unless the value of USBCMD[PSE]
equals that of USBSTS[PS].
The periodic schedule is used to manage all isochronous and interrupt transfer streams. The base of the
periodic schedule is the periodic frame list. Software links schedule data structures to the periodic frame
list to produce a graph of scheduled data structures. The graph represents an appropriate sequence of
transactions on the USB.
period of one are linked directly to the periodic frame list. Interrupt transfers (are managed with queue
heads) and isochronous streams with periods other than one are linked following the period-one
iTD/siTDs. Interrupt queue heads are linked into the frame list ordered by poll rate. Longer poll rates are
linked first (for example, closest to the periodic frame list), followed by shorter poll rates, with queue
heads with a poll rate of one, on the very end.
Freescale Semiconductor
FRINDEX[13–3]
Periodic Schedule
N+1
N+1
N+1
N+1
N+1
N+1
N+1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
N
Table 16-65. Operation of FRINDEX and SOFV (SOF Value Register)
Figure 16-47
Current
SOFV
N+1
N+1
N+1
N+1
N+1
N+1
N
N
FRINDEX[2–0]
illustrates isochronous transfers (using iTDs and siTDs) with a
111
000
001
010
011
100
101
110
FRINDEX[13–3]
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N+1
SOFV
Next
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N
Universal Serial Bus Interface
FRINDEX[2–0]
000
001
010
011
100
101
110
111
16-75