MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 222

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
Table 5-18
5.2.5
If two local access windows overlap, the lower numbered window takes precedence (see
window numbers). For instance, if two windows are set up as shown in
governs the mapping of the 1-Mbyte region from 0x7FF0_0000 to 0x7FFF_FFF, even though the window
described in local access window 7 also encompasses that memory region.
5.2.6
After a local access window is enabled, it should not be modified while any device in the system may be
using the window. Accordingly, a new window should not be used until the effect of the write to the
window is visible to all blocks that use the window. This can be guaranteed by completing a read of the
last local access window configuration register before enabling any other devices to use the window. For
instance, if local bus local access windows 1–3 are being configured in order during the initialization
process, the last write (to LBLAWAR3) should be followed by a read of LBLAWAR3 before any devices
try to use any of these windows. If the configuration is being done by the local e300c3 core, the read of
LBLAWAR3 should be followed by an isync instruction.
5.2.7
It is important to distinguish between the mapping function performed by the local access windows and
the additional mapping functions that happen at the target interface. The local access windows define how
a transaction is routed through the device internal interconnects from the transaction’s source to its target.
Once the transaction has arrived at its target interface, that interface controller may perform additional
mapping. For instance, the DDR SDRAM controller has chip select registers that map a memory request
to a particular external device. The local bus controller has base registers that perform a similar function.
The PCI interface has outbound address translation units that map the local address into an external address
space.
5-14
‘
RCWHR[ROMLOC]
RCWHR[RLEXT]/
Else
000
defines the reset value DDRLAWAR0[EN] and DDRLAWAR0[SIZE].
Precedence of Local Access Windows
Configuring Local Access Windows
Distinguishing Local Access Windows from Other Mapping
Functions
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Window
DDRLAWAR0[EN]
1
7
Reset Value
Table 5-19. Overlapping Local Access Windows
Table 5-18. DDRLAWAR0[EN] Reset Value
1
0
Base Address
0x7FF0_0000
0x0000_0000
e300c3 core boot performed from a DDR SDRAM device. DDR 8-Mbyte
(2
e300c3 core boot not performed from a DDR SDRAM device.
(22+1)
) local access window is enabled.
2 Gbytes
1 Mbyte
Size
Local bus
DDR SDRAM
Target Interface
Description
Table
5-19, local access window 1
Freescale Semiconductor
Table 5-1
for