MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 184

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Reset, Clocking, and Initialization
4.3.2.2.4
The device defines the default boot ROM address range to be 8 Mbytes at addresses 0x0000_0000 to
0x007F_FFFF or 0xFF80_0000 to 0xFFFF_FFFF (selected by the BMS reset configuration word field).
However, the on-chip peripheral that manages these boot ROM accesses can be selected at power up.
The boot ROM location reset configuration word field, shown in
boot ROM. The exact boot ROM location table to be used is defined by the setting of RCWHR[RLEXT]
bits, as shown in
address map are directed to the interface specified by this field.
The local access window of the selected boot ROM interface is enabled and initialized with the proper base
address and size, as described in
4-18
RCWHR
9–11
Bits
ROMLOC
Name
Field
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
When the boot sequencer is enabled, the e300 core must be prevented from
fetching boot code, by setting the core disable reset configuration word field
(COREDIS) as described in
High Register (RCWHR).”
sequencer should enable boot vector fetch by clearing ACR[COREDIS] as
described in
Boot ROM Location
Table
(Binary)
Value
4-11. Accesses to the boot vector and the default boot ROM region of the local
000
001
010
011
100
101
110
111
Section 6.2.1, “Arbiter Configuration Register (ACR).”
DDR SDRAM
PCI
Reserved, should be cleared.
Reserved, should be cleared.
Reserved
Local bus GPCM—8-bit ROM
Local bus GPCM—16-bit ROM
Reserved
Section 5.2, “Local Memory Map Overview and Example.”
Legacy Mode (RLEXT = 00)
Table 4-15. Boot ROM Location
If the e300 core is required to proceed, the boot
Section 4.3.2.2, “Reset Configuration Word
NOTE
Meaning
Table
Reserved
Local bus NAND Flash—8-bit small page
ROM
Reserved
Reserved
Reserved
Local bus NAND Flash—8-bit large page
ROM
Reserved
Reserved
4-15, establishes the location of
NAND Flash Mode (RLEXT = 01)
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