MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1203

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Index
EU
Exception little-endian mode, 7-17
Exception prefix, 7-18
Exceptions
External interrupt enable, 7-17
F
Features
Fetch register, 14-62
FIFO RAM controller, 16-46
Floating-point available, 7-18
Floating-point exception mode 0, 7-18
Floating-point exception mode 1, 7-18
Floating-point model
Force branch indirect on bus, 7-23
FPRn (floating-point registers 0–31), 7-16
FPSCR (floating-point status and control reg.), 7-16
FSTNs
G
G2
General Purpose I/O module (GPIO), see GPIO
General purpose timers (GTM), 5-48
Freescale Semiconductor
signals<$startmode, 15-8
TCP/IP off-load, 15-160–15-165
access, 14-65, 14-66
assignment status register, 14-67
overview, 7-30
overview of device features, 1-2
FP registers (FPRn), 7-16
FPRn (floating-point registers 0–31), 7-16
host controller operational model, 16-95
software operational model, 16-97
overview, 7-13
block diagram, 5-49
external signal description, 5-51
features, 5-49
functional description, 5-61
initialization/application information, 5-64
memory map/register definition, 5-52
modes of operation, 5-50
frame control blocks, 15-161
receive path off-load, 15-163
transmit path off-load, 15-161
capture modes, 5-61
cascaded modes, 5-62
general-purpose timer units, 5-61
reference modes, 5-61
capture, 5-51
cascaded, 5-50
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
GPCM (LBC general-purpose chip-select machine), 10-45
GPIO
GPRn (general-purpose registers 0–31), 7-16
H
Hash function, see eTSEC, hash function
HIDn (hardware implementation registers 0–2)
High BAT enable, 7-24
HRESET, 4-8
I
I/O sequencer, 13-1
I
2
C interface
overview, 5-48
registers, 5-54–5-60
see also Local bus controller (LBC)
block diagram, 21-1
features, 21-1
memory map/register definition, 21-2
overview, 21-1
registers, 21-3–21-5
signals, 21-2
PLL configuration, 7-23
block diagram, 11-1
features, 11-2
functional description, 11-6
memory map/register definition, 11-2–11-3
overview, 11-1
registers, 11-3–11-6
arbitration
block diagram, 17-1
boot sequencer mode, 4-23–4-25, 17-2, 17-15
calling address match condition, 17-5
clock control, 17-14
clock source, 5-50
reference, 5-50
PCI outbound address translation, 11-7
transaction forwarding, 11-6
transaction ordering, 11-8
arbitration control, 17-13
loss of arbitration—forcing of slave mode, 17-23
procedure for arbitration, 17-13
error condition behavior, 4-26, 17-16
clock stretching, 17-15
clock synchronization, 17-15
input synchronization and digital filter, 17-15
master mode, 17-14
from the CSB port, 11-7
from the DMA port, 11-7
from the PCI ports, 11-7
Index-5
F–I