MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 189

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

4.3.3.2
The device is capable of loading the reset configuration word from the I
I
configuration word from the I
I
of the device is still in reset state (HRESET asserted) to load the reset configuration words from an I
serial EEPROM.
Note that this does not prevent using the I
mode after reset state has completed. The only restriction is that the first two EEPROM data structures
contain dedicated reset information.
4.3.3.2.1
For a detailed description about the I
Sequencer Mode.”
If the I
EEPROM and reads the first two data structures (after reading the preamble). Upon being read, the reset
configuration words are latched inside the device and the I
is negated. There should be no other I
After HRESET is negated, the functional boot sequencer, in extended I
activated if the BOOTSEQ field of the reset configuration word high is set to 0b10.
4.3.3.2.2
The device uses 0b101_0000 for the EEPROM calling address. The EEPROM to be addressed must
contain the reset configuration information and be programmed to respond to this address. No additional
EEPROMs are accessed by the boot sequencer in reset configuration mode.
4.3.3.2.3
The I
be the first 3 bytes programmed into the EEPROM. It should have a value of 0xAA55AA. The I
checks to ensure that this preamble is correctly detected before proceeding further. Following the
preamble, there should be the two reset configuration words, programmed according to a particular format,
as shown in
The first 3 bytes hold the attributes and address offset. The addresses of the two reset configuration words
must be programmed to the offset of the reset configuration word low register (RCWLR) and reset
configuration word high register (RCWHR) respectively (see
Low Register (RCWLR),”
Freescale Semiconductor
2
2
C interfaces, but only I
C unit boot sequencer in a special mode. In this mode, the I
2
C module expects that a particular data format be used for data in the EEPROM. A preamble should
2
C interface is used for loading the reset configuration words, the I
Figure
Loading from I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Using the Boot Sequencer Reset Configuration
When reset configuration words are loaded from an I
serial EEPROM of extended addressing type must be used.
EEPROM Calling Address
EEPROM Data Format in Reset Configuration Mode
4-5.
2
C #1 can be used for this purpose). If the device is configured to load the reset
and
2
C interface, according to the reset configuration input signals, it uses the
Section 4.5.1.2, “Reset Configuration Word High Register
2
C EEPROM
2
2
C interface and the boot sequencer refer to
C traffic when the boot sequencer is active.
2
C boot sequencer to initiate the device in the normal functional
NOTE
2
C module enters its reset state until HRESET
2
Section 4.5.1.1, “Reset Configuration Word
C boot sequencer is activated while the rest
2
C EEPROM, an I
2
2
C addressing mode, may be
C interfaces (the device has two
2
C module addresses the
Reset, Clocking, and Initialization
Section 17.4.5, “Boot
2
C
(RCWHR)”).
2
C module
2
C
4-23