MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 628

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
13.4.2
PCI bus commands indicate the type of transaction occurring on the bus. These commands are encoded on
PCI_C/BE[3:0] during the address phase of the transaction. PCI bus commands are described in
Table
13-46
BE[3:0]
0b0000
0b0001
0b0010
0b0011
0b010x
0b0110
0b0111
0b100x
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
PCI_C/
13-45.
Interrupt acknowledge
Special cycle
I/O read
I/O write
—
Memory read
Memory write
—
Configuration read
Configuration write
Memory read multiple
Dual address cycle
Memory read line
Memory write and
invalidate
Bus Commands
Command Type
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Initiator Target
Supported as:
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
—
—
Table 13-45. PCI Command Definitions
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
—
—
A read implicitly addressed to the system interrupt controller. The size of
the vector to be returned is indicated on the byte enables after the
address phase.
Provides a simple message broadcast mechanism. See
Section 13.4.4.6, “Special Cycle Command,”
Accesses agents mapped in I/O address space.
Accesses agents mapped in I/O address space.
Reserved. No response occurs.
Accesses agents mapped in memory address space. A read from
prefetchable space, when seen as a target, fetches a cache line of data
(32 bytes) from the starting address, even though all 32 bytes may not
actually be sent to the initiator.
Accesses agents mapped in memory address space. Note that for
inbound writes less than 4-bytes, the PCI controller splits the transaction
into single byte writes to the target. Thus, the PCI interface cannot be
used to perform single beat writes to 16-bit devices on the local
peripheral interfaces.
Reserved. No response occurs.
Accesses the configuration space of each agent. An agent is selected
when its IDSEL signal is asserted. See
Configuration Access,”
As a target, a configuration read is only accepted if the PCI controller is
configured to be in agent mode.
Accesses the configuration space of each agent. An agent is selected
when its IDSEL signal is asserted. See
Configuration Access,”
write is only accepted if the PCI controller is configured to be in agent
mode.
Causes a prefetch of the next cache line.
Transfers an 8-byte address to devices.
Indicates that the initiator intends to transfer an entire cache line of data.
Indicates that the initiator will transfer an entire cache line of data, and if
PCI has any cacheable memory, this line needs to be invalidated.
for more information on configuration accesses.
for more information. As a target, a configuration
Definition
Section 13.4.4.4, “Host Mode
Section 13.4.4.4, “Host Mode
for more information.
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