MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 603

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 13-15
capability.
13.3.2.9
PCI_ECR contains fields for determining whether an interrupt or machine check is generated for the error
conditions reported in the PCI error status register (PCI_ESR). Note that if the corresponding bit in the
PCI error enable register (PCI_EER) is clear, the bit in the PCI error control register (PCI_ECR) has no
effect.
Figure 13-13
Freescale Semiconductor
Offset 0x20
Reset
Offset 0x24
Reset
0–28
W
Bits
W
R
R
29
30
31
1 = A machine check is generated.
0 = An interrupt is generated.
0
0
shows the bit settings of PCI_GCR. The bits that are not reserved have read and write
PCI Error Control Register (PCI_ECR)
shows the PCI_ECR fields.
SPRST
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
BBR
PPL
—
Reserved
Block bus requests. This bit could be used to prepare for entering a low-power mode by preventing
transactions on the PCI bus.
0 External bus requests are treated normally.
1 Block external bus requests. When this bit is set, all bus requests from external devices to the PCI
PCI pins low. This bit could be used to put the bus signals in a safe electrical state when the devices
on the bus are powered down. This bit should never be set during normal operation of the PCI bus.
0 PCI pins function normally
1 PCI pins in the low state. Setting this bit forces all the output and bidirectional pins of the PCI bus
Soft PCI reset. This bit provides software control of the PCI_RESET_OUT output signal. It is only
valid in host mode.
0 PCI_RESET_OUT is driven low.
1 PCI_RESET_OUT is driven high.
controller’s internal arbiter are blocked, and the bus is continuously granted to the PCI controller.
to be driven low.
Figure 13-12. PCI General Control Register (PCI_GCR)
Figure 13-13. PCI Error Control Register (PCI_ECR)
—
Table 13-15. PCI_GCR Field Descriptions
—
20
APAR PCISERR MPERR TPERR NORSP TABT
All zeros
All zeros
21
Description
22
23
24
28
25
Access: Read/Write
Access: Read/Write
BBR PPL SPRST
29
PCI Bus Interface
26
30
27
—
13-21
31
31