MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 453

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 10-2
Freescale Semiconductor
LSRCID[0:4]
LUPWAIT
LAD[0:15]
LCLK[0:1]
LCS[0:3]
LA[0:25]
LGPL3/
LGPL4/
Signal
LGPL5
LBCTL
LDVAL
LFWP
LFRB/
Name
LGTA/
LALE
shows the detailed external signal descriptions for the eLBC.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I/O
O
O
Function(s)
Table 10-2. Enhanced Local Bus Controller Detailed Signal Descriptions
Alternate
LUPWAIT
LGPL3
LGPL4
LFWP
External address latch enable. The local bus memory controller provides control for an external address
latch, which allows address and data to be multiplexed on the device pins.
Chip selects. Four chip selects are provided that are mutually exclusive.
Meaning
Meaning
LGTA
LFRB
—
—
—
—
—
—
—
State
State
Table 10-1. Signal Properties—Summary (continued)
Asserted/Negated—LALE is asserted with the address at the beginning of each memory
Asserted/Negated—Used to enable specific memory devices or peripherals connected to the
eLBC debug
eLBC debug
controller transaction. The number of cycles for which it is asserted is governed by the
ORn[EAD] and LCRR[EADC] fields. Note that no other control signals are asserted
during the assertion of LALE.
eLBC. LCS[0:3] are provided on a per-bank basis with LCS0 corresponding to the chip
select for memory bank 0, which has the memory type and attributes defined by BR0 and
OR0.
GPCM
Mode
UPM
FCM
FCM
UPM
UPM
UPM
—
—
—
—
General purpose line 3
Flash write protect
Transaction termination
Flash ready/busy, open-drain shared pin
General purpose line 4
External device wait
General purpose line 5
Data buffer control
Non-multiplexed address bus
Multiplexed address/data bus
Local bus clocks
Local bus data valid
Local bus source ID
Descriptions
Description
Signals
No. of
Enhanced Local Bus Controller
26
16
1
1
1
1
1
1
1
1
2
1
5
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
Reset State
(Outputs)
Reset_cfg
Reset_cfg
High-Z
Driven
10-5