MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 470

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.3.1.5
The refresh timer prescaler register (MRTPR), shown in
provide the UPM refresh timers clock.
Table 10-12
10.3.1.6
The memory data register (MDR), shown in
from the RAM array for UPM read or write commands. MDR also contains data written to or read from
an external NAND Flash EEPROM for FCM write address, write data, and read status commands. MDR
10-22
18–21
22–25
26–31
Offset 0x0_5084
Reset
8–31
Bits
Bits
0–7
W
R
0
Name
Name
MAD
WLF
PTP
TLF
—
describes MRTPR fields.
Memory Refresh Timer Prescaler Register (MRTPR)
UPM/FCM Data Register (MDR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Write loop field. Determines the number of times a loop defined in the UPM n will be executed for a burst- or
single-beat write pattern.
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Refresh loop field. Determines the number of times a loop defined in the UPM n will be executed for a refresh
service pattern.
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Machine address. RAM address pointer for the command executed. This field is incremented by 1, each time
the UPM is accessed and the OP field is set to WRITE or READ. Address range is 64 words per UPM n .
Refresh timers prescaler. Determines the period of the refresh timers input clock. The system clock is divided
by PTP except when the value is 00000_0000, which represents the maximum divider of 256.
Reserved
PTP
Figure 10-8. Memory Refresh Timer Prescaler Register (MRTPR)
Table 10-11. M
7
8
Table 10-12. MRTPR Field Descriptions
x
MR Field Descriptions (continued)
Figure 10-9
All zeros
Description
Description
Figure
and
Figure
10-8, is used to divide the system clock to
—
10-10, contains data written to or read
Freescale Semiconductor
Access: Read/Write
31