MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 171

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

All of these reset sources are fed into the reset controller and, depending on the source of the reset, different
actions are taken. The reset status register, described in
indicates the last sources to cause a reset.
4.2.1.1
Table 4-3
4.2.1.2
The reset control logic determines the cause of reset, synchronizes it if necessary, and resets the
appropriate internal hardware. The SRESET input is not routed to the reset control logic, but directly to
the sreset input on the e300 core. Each reset flow has a different impact on the device logic:
The memory controller, system protection logic, interrupt controller, and I/O signals are initialized only
on hard reset. A soft reset causes a reset exception to the e300 core but does not reset other device logic.
Table 4-4
Freescale Semiconductor
Power-on reset
(PORESET)
Hard reset (HRESET)
Soft reset (SRESET)
Software watchdog reset
System bus monitor reset
Checkstop reset
JTAG reset
Software hard reset
•
•
•
•
•
JTAG reset
Software hard reset
Power-on reset has the greatest impact, resetting the entire device, including clock logic and error
capture registers.
Hard reset resets the entire device excluding clock logic and error capture registers.
Soft reset initializes the internal logic while maintaining the system configuration.
Name
describes reset causes.
identifies the reset actions for each reset source.
Reset Causes
Reset Actions
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Input signal. Asserting this signal initiates the power-on reset flow that resets the entire device and
configures various attributes of the device including its clock modes.
A bidirectional I/O signal. The device can detect an external assertion of HRESET only while it is
not asserting hard reset. HRESET is an open-drain signal.
Input signal. Connected to the sreset input of the e300 core, and when asserted, causes a high
priority interrupt to the e300 core.
After the device watchdog counts to zero, a software watchdog reset is signaled. The enabled
software watchdog event then generates an internal hard reset sequence.
After the device CSB bus monitor reaches a timeout condition, a bus monitor reset is asserted.
The enabled bus monitor event then generates an internal hard reset sequence.
If the core enters checkstop state and the checkstop reset is enabled (RMR[CSRE] = 1), the
checkstop reset is asserted. The enabled checkstop event then generates an internal hard reset
sequence.
When JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated.
A hard reset sequence can be initialized by writing to a memory-mapped register (RCR).
Table 4-3. Reset Causes
Section 4.5.1.3, “Reset Status Register (RSR),”
Description
Reset, Clocking, and Initialization
4-5