MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1065

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

On the successful completion of the packet(s) described by the dTD, the active bit in the dTD will be
cleared and the next pointer will be followed when the Terminate bit is clear. When the Terminate bit is
set, the USB_DR will flush the endpoint/direction and cease operations for that endpoint/direction.
On the unsuccessful completion of a packet (see long packet above), the dQH will be left pointing to the
dTD that was in error. In order to recover from this error condition, the DCD must properly re-initialize
the dQH by clearing the active bit and update the nextTD pointer before attempting to re-prime the
endpoint.
There is no required interaction with the DCD for handling such errors.
16.8.3.4.1
Freescale Semiconductor
•
•
A short packet (number of bytes < maximum packet length) was received. *** This is a successful
transfer completion; DCD must check Total Bytes in dTD to determine the number of bytes that
are remaining. From the total bytes remaining in the dTD, the DCD can compute the actual bytes
received.
A long packet was received (number of bytes > maximum packet size) OR (total bytes received >
total bytes specified). *** This is an error condition. The device controller will discard the
remaining packet, and set the Buffer Error bit in the dTD. In addition, the endpoint will be flushed
and the USBERR interrupt will become active.
1
2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Force Bit Stuff Error.
NYET/ACK—NYET unless the Transfer Descriptor has packets remaining according to the USB
variable length protocol then ACK.
SYSERR—System error should never occur when the latency FIFOs are correctly sized and
the DCD is responsive.
All packet level errors such as a missing handshake or CRC error will be
retried automatically by the device controller.
Interrupt/Bulk Endpoint Bus Response Matrix
Invalid
Setup
Ping
Out
In
Table 16-88. Interrupt/Bulk Endpoint Bus Response Matrix
STALL
STALL
STALL
Ignore
Ignore
Stall
Primed
Ignore
Ignore
NAK
NAK
NAK
Not
Receive + NYET/ACK
NOTE
Transmit
Primed
Ignore
Ignore
ACK
2
Underflow
BS Error
Ignore
N/A
N/A
N/A
1
Universal Serial Bus Interface
Overflow
Ignore
NAK
N/A
N/A
N/A
16-137