MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 472

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
UPM special operation modes are set in registers MxMR[OP], see
Registers (MxMR).”
Mode Register (FMR).”
performing a dummy access to a bank associated with the controller in question, but use of LSOR avoids
changing settings for the address space occupied by the bank. More details of special operation sequences
appear in
Table 10-14
10.3.1.8
The UPM refresh timer (LURT), shown in
selected a UPM machine and are refresh-enabled (M
qualified bank generates a refresh request using the selected UPM. The qualified banks rotate their
requests.
10-24
29–31
Offset 0x0_5090
Offset 0x0_50A0
Reset
0–28
Reset
Bits
W
W
R
R
0
0
Name
BANK Bank on which a special operation is initiated. If the bank identified by BANK is marked valid (BR n [V] set) and
Section 10.4.4.2.1, “UPM Programming Example (Two Sequential Writes to the RAM Array).”
—
describes LSOR.
UPM Refresh Timer (LURT)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
the bank is controlled by a memory controller whose current mode OP is non-zero—or a special
operation—eLBC will request the special operation to be activated on the selected bank when this field is
written. Otherwise, writing this field has no effect.
000 Bank 0 is triggered for special operation
...
011 Bank 3 is triggered for special operation
100–111Reserved
LURT
FCM special operation modes are set in FMR[OP], see
Figure 10-11. Special Operation Initiation Register (LSOR)
Writing LSOR has the same effect as setting a special controller mode and
7
8
Figure 10-12. UPM Refresh Timer (LURT)
Table 10-14. LSOR Field Description
Figure
10-12, generates a refresh request for all valid banks that
—
All zeros
All zeros
x
MR[RFEN] = 1). Each time the timer expires, a
Description
Section 10.3.1.4, “UPM Mode
—
Section 10.3.1.17, “Flash
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
28 29
BANK
31
31