MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 339

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
12–15
Bits
10
11
16
2
3
4
5
6
7
8
9
SBCLK
SLEEP
Name
DOZE
ECLK
DPM
EBD
NAP
EBA
PAR
ICE
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Enable ap_in[0:3] and ape for address parity checking.
0 Disables address parity checking during a snoop operation
1 Allows an address parity error during snoop operations to cause a checkstop if MSR[ME] = 0 or a
Enable dpe for data parity checking.
0 Disables data parity checking
1 Allows a data parity error during reads to cause a checkstop if MSR[ME] = 0 or a machine check
clk_out output enable. Used in conjunction with HID0[ECLK] and hreset to configure clk_out. See
Table 7-3
Reserved, should be cleared
clk_out output enable. Used in conjunction with HID0[SBCLK] and the hreset signal to configure
clk_out. See
Disable precharge of artry_out
0 Precharge of artry_out enabled
1 Alters bus protocol slightly by preventing the processor from driving artry_out to high (negated) state.
Doze mode enable. Operates in conjunction with MSR[POW].
0 Doze mode disabled
1 Doze mode enabled. Doze mode is invoked by setting MSR[POW] while this bit is set. In doze mode,
Nap mode enable. Operates in conjunction with MSR[POW].
0 Nap mode disabled
1 Nap mode enabled. Nap mode is invoked by setting MSR[POW] while this bit is set. In nap mode, the
Sleep mode enable. Operates in conjunction with MSR[POW].
0 Sleep mode disabled
1 Sleep mode enabled. Sleep mode is invoked by setting MSR[POW] while this bit is set. qreq is
Dynamic power management enable
0 Dynamic power management is disabled
1 Functional units enter a low-power mode automatically if the unit is idle. This does not affect
Reserved, should be cleared.
Instruction cache enable
0 The instruction cache is neither accessed nor updated. All pages are accessed as if they were
1 The instruction cache is enabled
machine check interrupt if MSR[ME] = 1
interrupt if MSR[ME] = 1
If this is done, the integrated device must restore the signals to the high state.
the PLL, time base, and snooping remain active.
PLL and time base remain active.
asserted to indicate that the processor is ready to enter sleep mode. If the system logic determines
that the processor may enter sleep mode, the quiesce acknowledge signal, qack, is asserted back to
the processor. Once qack assertion is detected, the processor enters sleep mode after several
processor clocks. At this point, the system logic may turn off the PLL by first configuring pll_cfg[0:6]
to PLL bypass mode, then disabling sysclk .
operational performance and is transparent to software or any external hardware.
marked cache-inhibited (WIM = x1x). Potential cache accesses from the bus (snoop and cache
operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits are ignored
and all instruction fetches are propagated to the coherent system bus (CSB) as single-beat
transactions. For those transactions, however, ci reflects the state of the I bit in the MMU for that page
regardless of cache disabled status. ICE is zero at power-up.
Table 7-2. e300 HID0 Bit Descriptions (continued)
for settings.
Table 7-3
for settings.
Function
e300 Processor Core Overview
7-21