MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 128

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Memory Map
2-24
0x2_46AC
0x2_46BC
0x2_46CC
0x2_46DC
0x2_46EC
0x2_46FC
0x2_46A0
0x2_46A4
0x2_46A8
0x2_46B0
0x2_46B4
0x2_46B8
0x2_46C0
0x2_46C4
0x2_46C8
0x2_46D0
0x2_46D4
0x2_46D8
0x2_46E0
0x2_46E4
0x2_46E8
0x2_470C
0x2_471C
0x2_46F0
0x2_46F4
0x2_46F8
0x2_4700
0x2_4704
0x2_4708
0x2_4710
0x2_4714
0x2_4718
0x2_4720
0x2_4724
Offset
RPKT—Receive packet counter
RFCS—Receive FCS error counter
RMCA—Receive multicast packet counter
RBCA—Receive broadcast packet counter
RXCF—Receive control frame packet counter
RXPF—Receive PAUSE frame packet counter
RXUO—Receive unknown OP code counter
RALN—Receive alignment error counter
RFLR—Receive frame length error counter
RCDE—Receive code error counter
RCSE—Receive carrier sense error counter
RUND—Receive undersize packet counter
ROVR—Receive oversize packet counter
RFRG—Receive fragments counter
RJBR—Receive jabber counter
RDRP—Receive drop counter
TBYT—Transmit byte counter
TPKT—Transmit packet counter
TMCA—Transmit multicast packet counter
TBCA—Transmit broadcast packet counter
TXPF—Transmit PAUSE control frame counter
TDFR—Transmit deferral packet counter
TEDF—Transmit excessive deferral packet counter
TSCL—Transmit single collision packet counter
TMCL—Transmit multiple collision packet counter
TLCL—Transmit late collision packet counter
TXCL—Transmit excessive collision packet counter
TNCL—Transmit total collision counter
Reserved
TDRP—Transmit drop frame counter
TJBR—Transmit jabber frame counter
TFCS—Transmit FCS error counter
TXCF—Transmit control frame counter
TOVR—Transmit oversize frame counter
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Register
Table 2-2. Memory Map (continued)
eTSEC Transmit Counters
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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