MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 266

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
5.7.5.2
The global timers mode registers (GTMDR1, GTMDR2, GTMDR3, and GTMDR4) are shown in
Figure
Erratic behavior may occur if GTCFR1 and GTCFR2 are not initialized before the GTMDRn. Only
GTCFRn[RSTn] and GTCFRn[STPn] can be modified at any time.
Table 5-59
5-58
Offset
Bits
0–7
8–9
10
11
12
Reset
W
R
5-42.
0x10(GTMDR1)
0x12(GTMDR2)
Name
SPS
FRR
ORI
OM
CE
0
defines the bit fields of GTMDR.
Global Timers Mode Registers (GTMDR1–GTMDR4)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Secondary prescaler value
The secondary prescaler is programmed to divide the clock input to corresponding timer by values from 1 to
256. The value 0x00 divides the clock by 1 and 0xFF divides the clock by 256.
Capture edge and enable interrupt
00 Disable interrupt on capture event; capture function is disabled
01 Capture on rising TIN n edge only and enable interrupt on capture event.
10 Capture on falling TIN n edge only and enable interrupt on capture event.
11 Capture on any TIN n edge and enable interrupt on capture event.
Note: The frequency of TIN n should be slower than system clock (TIN n is sampled internally by system clock
Output mode
0 Toggle TOUT n every time when the corresponding timer matches its reference value.
1 Active-low pulse on TOUT n for one timer input clock cycle (4 input clock cycles for the system clock) as
Note: TOUT n changes are internally synchronized to the rising edge of the system clock
Output reference interrupt enable
0 Disable interrupt for reference reached (does not affect interrupt on capture function).
1 Enable interrupt on reaching the reference value.
Free run/restart mode
0 Free run. The timer count continues to increment after the reference value is reached.
1 Restart. The timer count is reset immediately after the reference value is reached.
defined by the ICLK n bits. Thus, TOUT n may be low for four general system clocks, one general system
slow go clock period, or one TIN n pin clock cycle period.
to detect TIN n ’s rising/falling edge before updating the counter)
Figure 5-42. Global Timers Mode Registers (GTMDR1
SPS
0x20(GTMDR3)
0x22(GTMDR4)
Table 5-59. GTMDR Bit Settings
7
All zeros
Description
8
CE
9
OM
10
–
GTMDR4)
ORI
11
FRR
12
Freescale Semiconductor
Access: Read/Write
13
ICLK
14
GE
15