MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 179

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

4.3.2.1
RCWLR is shown in
word low loaded during the reset flow.
Table 4-8
4.3.2.1.1
The system PLL ratio reset, shown in
signal and the internal csb_clk of the device. csb_clk drives internal units and feeds the e300 core PLL.
Freescale Semiconductor
16–31
9–15
Bits
2–3
4–7
0
1
8
Field LBCM
Field
COREPLL Core PLL configuration. COREPLL sets the ratio between the e300 core clock and the internal csb_clk of
DDRCM
defines the RCWLR bit fields.
Name
LBCM
SPMF
16
—
—
—
0
Reset Configuration Word Low Register (RCWLR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
System PLL Configuration
DDRCM
Local bus memory controller clock mode. Selects the local bus controller clock ratio. The local bus
memory controller operates with a frequency equal to the frequency of csb_clk . This bit should be cleared.
DDR SDRAM memory controller clock mode. Selects the DDR SDRAM memory controller clock ratio.
The DDR SDRAM memory controller operates at twice the frequency of the csb_clk .
0 csb_clk ratio is 1:1
1 csb_clk ratio is 2:1
Reserved. Must be configured as 2’b10.
System PLL multiplication factor.
See
Reserved, should be cleared
the device. The encodings for COREPLL are given in the hardware specifications for this device.
Reserved, should be cleared.
1
Figure
Figure 4-3. Reset Configuration Word Low Register (RCWLR)
Section ,
2
4-3. This read-only register gets its values according to the reset configuration
—
“,” for more information.
3
Table 4-8. RCWLR Bit Settings
4
Table
SPMF
4-9, establishes the clock ratio between the SYS_CLK_IN
7
—
Description
—
8
9
Reset, Clocking, and Initialization
COREPLL
15
31
4-13