MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 52

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

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USB Interface Block Diagram .............................................................................................. 16-2
Capability Registers Length (CAPLENGTH)....................................................................... 16-8
Host Controller Interface Version (HCIVERSION) ............................................................. 16-8
Host Controller Structural Parameters (HCSPARAMS)....................................................... 16-9
Host Control Capability Parameters (HCCPARAMS) ....................................................... 16-10
Device Interface Version (DCIVERSION) ......................................................................... 16-11
Device Control Capability Parameters (DCCPARAMS).................................................... 16-11
USB Command Register (USBCMD) ................................................................................ 16-12
USB Status Register (USBSTS).......................................................................................... 16-14
USB Interrupt Enable (USBINTR) ..................................................................................... 16-17
USB Frame Index (FRINDEX)........................................................................................... 16-19
Periodic Frame List Base Address (PERIODICLISTBASE) ............................................. 16-20
Device Address (DEVICEADDR)...................................................................................... 16-20
Current Asynchronous List Address (ASYNCLISTADDR) .............................................. 16-21
Endpoint List Address (ENDPOINTLISTADDR).............................................................. 16-21
Master Interface Data Burst Size (BURSTSIZE) ............................................................... 16-22
Transmit FIFO Tuning Controls (TXFILLTUNING) ......................................................... 16-23
ULPI Register Access (ULPI VIEWPORT) ....................................................................... 16-24
Configure Flag Register (CONFIGFLAG) ......................................................................... 16-26
Port Status and Control (PORTSC)..................................................................................... 16-26
OTG Status Control (OTGSC)............................................................................................ 16-32
USB Mode (USBMODE) ................................................................................................... 16-34
Endpoint Setup Status (ENDPTSETUPSTAT) ................................................................... 16-35
Endpoint Initialization (ENDPTPRIME) ............................................................................ 16-35
Endpoint Flush (ENDPTFLUSH) ....................................................................................... 16-36
Endpoint Status (ENDPTSTATUS)..................................................................................... 16-36
Endpoint Complete (ENDPTCOMPLETE) ........................................................................ 16-37
Endpoint Control 0 (ENDPTCTRL0) ................................................................................. 16-38
Endpoint Control 1 to 5 (ENDPTCTRLn) .......................................................................... 16-39
Snoop 1 and Snoop 2 (SNOOPn)........................................................................................ 16-40
Age Count Threshold (AGE_CNT_THRESH)................................................................... 16-42
Priority Control (PRI_CTRL) ............................................................................................. 16-42
System Interface Control Register (SI_CTRL)................................................................... 16-43
USB General-Purpose Register (CONTROL) .................................................................... 16-44
Periodic Schedule Organization.......................................................................................... 16-48
Frame List Link Pointer Format.......................................................................................... 16-48
Asynchronous Schedule Organization ................................................................................ 16-49
Isochronous Transaction Descriptor (iTD) ......................................................................... 16-50
Split-Transaction Isochronous Transaction Descriptor (siTD) ........................................... 16-53
Queue Element Transfer Descriptor (qTD)......................................................................... 16-57
Queue Head Layout ............................................................................................................ 16-62
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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