MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 933

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.2.3
The USBDR_CLK input provides the clocking signal for the ULPI PHY interface. The clock is 60 MHz.
Detailed clock specifications are given in the appropriate hardware specifications document.
16.3
This section provides the memory map and detailed descriptions of all USB interface registers. The
memory map of the USB interface is shown in
Freescale Semiconductor
USBDR_TXRXD[7:0]
USBDR_PWRFAULT
USBDR_PCTL0
USBDR_PCTL1
USBDR_STP
Signal
Memory Map/Register Definitions
PHY Clocks
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I/O
I/O Data bit n . USBDR_TXRXD n is bit n of the 8-bit (USBDR_TXRXD7–USBDR_TXRXD0),
O Stop. USBDR_STP indicates the end of a transfer on the bus.
O Port control 0. USBDR_PCTL0 controls the port status indicator LED 0 when in host mode.
O Port control 1. USBDR_PCTL1 controls the port status indicator LED 1 when in host mode.
I
Vbus.
uni-directional data bus used to carry USB, register, and interrupt data between the PHY and
the USB controller.
Power fault. USBDR_PWRFAULT indicates whether a power fault occurred on the USB port
Meaning
Meaning
Meaning
Meaning
Meaning
Timing
Timing
Table 16-2. ULPI Signal Descriptions (continued)
Timing Synchronous to PHY_CLK.
Timing Synchronous to PHY_CLK.
Timing Synchronous to PHY_CLK.
State
State
State
State
State
Asserted—USB asserts this signal for 1 clock cycle to stop the data stream
Negated—Indicates normal operation.
Asserted—Indicates that a Vbus fault occurred. Applications that support power
Negated—Indicates normal operation.
Asserted—LED on.
Negated—LED off.
Synchronous to PHY_CLK.
Asserted—LED on.
Negated—LED off.
Synchronous to PHY_CLK.
Asserted—Data bit n is 1.
Negated—Data bit n is 0.
currently on the bus. If USB port is sending data to the PHY, USBDR_STP
indicates the last byte of data was previously on the bus. If the PHY is
sending data to USB port, USBDR_STP forces the PHY to end its transfer,
negate USBDR_DIR and relinquish control of the data bus to the USB port.
switching must shut down Vbus power.
Table
16-3.
Description
Universal Serial Bus Interface
16-5