MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 924

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15-206
Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
Set up the MII Mgmt for a read cycle to the PHY MII Mgmt register (write the PHY address and Register address),
This enables the TBI to restart Auto-Negotiations using the configuration set in the AN Advertisement register.
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)
Set up the MII Mgmt for a write cycle to TBI’s Control register (write the PHY address and Register address),
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_00x_x110_0000]
read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx’d)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
The control register (CR) is at offset address 0x00 from the TBI’s address. (in this case 0x10)
The PHY Status control register is at address 0x1 and in this case the PHY Address is 0x10.
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)
(Uses the PHY address (0x10) and Register address (6) placed in MIIMADD register),
(Uses the PHY address (0x10) and Register address (5) placed in MIIMADD register),
(Uses the PHY address (2) and Register address (2) placed in MIIMADD register),
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
Writing to MII Mgmt Control with 16-bit data intended for TBI’s Control register,
Table 15-176. RTBI Mode Register Initialization Steps (continued)
Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0110]
Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0101]
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0001]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Perform an MII Mgmt read cycle of AN Expansion Register.
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
read the MIIMSTAT register and check bit 10 (AN Done)
Check to see if PHY has completed Auto-Negotiation.
Perform an MII Mgmt read cycle of Status Register.
This indicates that the write cycle was completed.
Check to see if MII Mgmt write is complete.
Perform an MII Mgmt write cycle to TBI.
Initialize MACnADDR1/2 (Optional)
Clear MIIMCOM[Read Cycle]
Clear MIIMCOM[Read Cycle]
Clear MIIMCOM[Read Cycle]
Initialize GADDR n (Optional)
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
When MIIMIND[BUSY]=0,
When MIIMIND[BUSY]=0,
Initialize IMASK (Optional)
Clear IEVENT register,
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