MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1207

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Index
MDM[0:8] (DDR SDRAM data output mask) signals, 9-7
MDQ[0:8] (DDR data bus strobe) signals, 9-5, 9-30
MDVAL (DDR/LBC debug mode data valid) signal, 10-7
Memory accesses, 7-37
Memory management unit (MMU)
Memory maps
Message digest execution unit (MDEU), 14-28
MODT[0:3] (DDR on-die termination) signals, 9-7
MPC603e core, see e300 core
MRAS (DDR row address strobe) signal, 9-6
MSR (machine state register), 7-17
MSRCID[0:4] (DDR/LBC debug source ID) signals, 10-7
MWE (DDR write enable) signal, 9-7
N
No-op the data cache touch instructions, 7-23
Freescale Semiconductor
overview, 7-9, 7-34
accessing CCSR memory from external masters, 5-16
address translation and mapping, 5-3
complete IMMR map, 2-1
configuring local access windows, 5-14
CSB arbiter and bus monitor, 6-2
DDR controller, 9-8
distinguishing local access windows from other mapping
DMA/messaging unit, 12-2
DUART, 18-4–18-5
eTSEC, 15-11
general purpose timers, 5-52
GPIO, 21-2
I/O sequencer, 11-2–11-3
I
inbound address translation and mapping windows, 5-15
IPIC, 8-6–8-7
LBC, 10-7
local access register, 5-4
local access windows
outbound address translation and mapping windows, 5-15
PCI, 13-11
periodic interval timer, 5-44
power management control, 5-65
real time clock module, 5-37
reset, 4-32
SPI, 19-8
USB interface, 16-5
watchdog timer, 5-30
window into configuration space, 5-4
2
C, 17-4
intoduction, 5-4
precedence, 5-14
functions, 5-14
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
P
PCI
address map
block diagram, 13-1
bridge
bus arbitration, 13-43
bus arbitration unit, 1-13
bus commands, 13-46
bus error functions, 13-57
bus operations, 13-53
CompactPCI Hot Swap specification support, 13-60
DMA controller, see DMA/messaging unit, DMA
features, 13-3
functional description, 13-43
inbound address translation, 13-59
inbound windows, 5-15
initialization/application information, 13-60
memory map/register definition, 13-11
modes of operation, 13-3
output hold configuration, 4-21
overview, 1-12
protocol fundamentals, 13-47
address translation
arbitration example, 13-45
PCI parity operation, 13-58
alogrithm, 13-44
broken master lock-out, 13-45
master latency timer, 13-45
parking, 13-44
parity, 13-57
reporting, 13-57
agent mode configuration access, 13-55
data streaming, 13-54
dual address cycles, 13-54
fast back-to-back transactions, 13-53
host mode configuration access, 13-54
interrupt acknowledge, 13-56
special cycle command, 13-55
sequence for agent mode, 13-60
sequence for host mode, 13-60
host/agent mode configuration, 13-3
PCI arbiter configuration, 13-4
addressing, 13-47
basic transfer control, 13-47
bus driving and turnaround, 13-48
bus transactions, 13-49
byte enable signals, 13-48
device selection, 13-48
PCI outbound, 11-7
controller
Index-9
N–P