MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 42

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

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8-26
9-1
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9-26
9-27
9-28
9-29
9-30
9-31
9-32
9-33
10-1
xlii
System Internal Interrupt Force Register (SIFCR_L)........................................................... 8-25
System External Interrupt Force Register (SEFCR) ............................................................. 8-26
System Error Status Register (SERFR)................................................................................. 8-26
System Critical Interrupt Vector Register (SCVCR) ............................................................ 8-27
System Management Interrupt Vector Register (SMVCR)................................................... 8-28
Interrupt Structure ................................................................................................................. 8-29
DDR Interrupt Request Masking .......................................................................................... 8-35
DDR Memory Controller Simplified Block Diagram............................................................. 9-2
Chip Select Bounds Registers (CSn_BNDS).......................................................................... 9-9
Chip Select Configuration Register (CSn_CONFIG) ........................................................... 9-10
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) ................................................ 9-12
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) ................................................ 9-12
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) ................................................ 9-14
DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2).................................. 9-16
DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) .............................. 9-18
DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)....................... 9-21
DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)............................. 9-22
DDR SDRAM Mode 2 Configuration Register (DDR_SDRAM_MODE_2)...................... 9-23
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL) ................................ 9-24
DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL) .................. 9-26
DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)................. 9-27
DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)....... 9-27
DDR Initialization Address Configuration Register (DDR_INIT_ADDR) ......................... 9-28
DDR IP Block Revision 1 (DDR_IP_REV1) ....................................................................... 9-28
DDR IP Block Revision 2 (DDR_IP_REV2) ....................................................................... 9-29
DDR Memory Controller Block Diagram ............................................................................ 9-30
Typical Dual Data Rate SDRAM Internal Organization....................................................... 9-31
Typical DDR SDRAM Interface Signals .............................................................................. 9-31
Example 64-Mbyte DDR SDRAM Configuration................................................................ 9-32
DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 ........................ 9-40
DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTOR ............................... 9-41
DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3...................... 9-41
DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs .................................... 9-42
DDR SDRAM Mode-Set Command Timing ........................................................................ 9-42
Registered DDR SDRAM DIMM Burst Write Timing ........................................................ 9-43
Write Timing Adjustments Example for Write Latency = 1 ................................................. 9-44
DDR SDRAM Bank Staggered Auto Refresh Timing.......................................................... 9-45
DDR SDRAM Power-Down Mode ...................................................................................... 9-46
DDR SDRAM Self-Refresh Entry Timing ........................................................................... 9-47
DDR SDRAM Self-Refresh Exit Timing ............................................................................. 9-47
Enhanced Local Bus Controller Block Diagram................................................................... 10-1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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