MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 673

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

14.4.2.2
The most common task likely to be executed through the MDEU is HMAC generation. HMACs are used
to provide message integrity within a number of security protocols, including IPSec, and TLS. The SSL
3.0 protocol uses a slightly different ‘SSL-MAC’. If an HMAC or SSL-MAC is to be performed using a
single descriptor (with the MDEU acting as sole or secondary EU), the following mode register bit settings
should be used:
To generate an HMAC for a message that is spread across a sequence of descriptors, the following mode
register bit settings should be used:
Freescale Semiconductor
62–63
Bits
58
59
60
61
SMAC
HMAC
Name
EALG
ALG
INIT
Table 14-19. Mode Register—HMAC or SSL-MAC Generated by Single Descriptor
Recommended Settings for MDEUMR
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Specifies whether to perform an SSL-MAC operation
0 Normal operation
1 Perform an SSL3.0 MAC operation. This requires a key and key length. If this is set then the HMAC bit
Initialization bit. Most operations will require this bit to be set. Cleared only for operations that load context
from a known intermediate hash value.
0 Do not initialize digest registers. In this case the registers must be loaded from a hash context pointer in
1 Do an algorithm-specific initialization of the digest registers.
Specifies whether to perform an HMAC operation
0 Normal operation
1 Perform an HMAC operation. This requires a key and key length. If this is set then the SMAC bit should
The EALG (Extended Algorithm bit) and ALG (Algorithm) bits together specify the message digest
algorithm, as follows:
000 SHA-160 algorithm (full name for SHA-1)
001 SHA-256 algorithm
010 MD5 algorithm
011 SHA-224 algorithm
Others: Reserved
should be 0.
the descriptor. When the data to be hashed is spread across multiple descriptors, this bit is set on all but
the first descriptor.
be 0.
Table 14-18. MDEUMR in ‘New’ Configuration (continued)
Bits
56
58
59
60
HMAC
CONT
SMAC
Field
INIT
For HMAC
0 (off)
0 (on)
1 (on)
1(on)
Description
Value
For SSL-MAC
0 (off)
0 (on)
1(on)
1(on)
Security Engine (SEC) 2.2
14-31