MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 212

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
5.2.2
The internal memory map registers’ base address register (IMMRBAR) defines a window that is used to
access all memory-mapped configuration, control, and status registers, referred to as internal memory map
registers or IMMR. This window is always enabled with a fixed size of 1 Mbyte, and no other attributes
are attached so there is no associated size/attribute register. This window always takes precedence over all
local access windows. The IMMRBAR always come out of reset with a default base address value of
0xFF40_0000, and this base address value can be modified by writing to this register. For more
information, see
5.2.3
As demonstrated in the address map overview in
Example,”
interface. This allows the internal interconnections of the device to route a transaction from its source to
the proper target. No address translation is performed. The base address defines the high order address bits
that give the location of the window in the local address space. The window attributes enable the window
and define its size, while the window number specifies the target interface.
With the exception of configuration space (mapped by IMMRBAR), all addresses used by the system must
be mapped by a local access window. This includes addresses that are mapped by PCI inbound windows.
The local access window registers exist as part of the local access block in the system configuration
registers. See
window registers is given in the following sections. Note that the minimum size of a window is 4 Kbytes,
so the low order 12 bits of the base address cannot be specified.
5.2.3.1
Table 5-4
5-4
Local Memory
Offset (Hex)
0x0_000C–
0x0_001C
0x0_0000
0x0_0004
0x0_0008
0x0_0020
shows the memory map for the local access registers.
local access windows associate a range of the local 32-bit address space with a particular target
Window into Configuration Space
Local Access Windows
Local Access Register Memory Map
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Section 5.3.2, “System Configuration Registers.”
Although it is legal to use the 3-Mbyte space consecutive to the 1 Mbyte of
the IMMR (for example, if IMMRBAR is 0xFF40_0000, the 3-Mbyte
address space consecutive to it is 0xFF50_0000–0xFF7F_FFFF), it is not
recommended. This space may be used in future derivatives of the device
that require a larger internal memory space.
Internal memory map base address register (IMMRBAR)
Reserved
Alternate configuration base address register (ALTCBAR)
Reserved
eLBC local access window 0 base address register (LBLAWBAR0)
Section 5.2.4.1, “Internal Memory Map Registers Base Address Register (IMMRBAR).”
Table 5-4. Local Access Register Memory Map
Register
NOTE
Section 5.2, “Local Memory Map Overview and
A detailed description of the local access
Access
R/W
R/W
R/W
—
—
0x0000_0000
0xFF40_0000
0x0000_0000
Reset
—
—
Freescale Semiconductor
1
Section/Page
5.2.4.1/5-6
5.2.4.2/5-7
5.2.4.3/5-8
—
—