MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 643

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MPC8313CZQADDC

Manufacturer Part Number
MPC8313CZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8313CZQADDC

Processor Series
MPC8313
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8313CZQADDC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 14
Security Engine (SEC) 2.2
This chapter describes the functionality of the integrated security engine (SEC 2.2) in the MPC8313E. It
addresses the following topics:
The SEC 2.2 is designed to off-load computationally intensive security functions, such as authentication,
and bulk encryption from the processor core of the MPC8313E. It is optimized to process all the algorithms
associated with IPSec, SSL/TLS, iSCSI, SRTP, and 802.11i. The SEC 2.2 is derived from integrated
security cores found in other members of the PowerQUICC family, including SEC 1.0, the version
implemented in the MPC8272 and SEC 2.0, implemented on the MPC8555.
The security engine’s execution units (EUs) and primary features include the following:
Freescale Semiconductor
Section 14.1, “SEC 2.2 Architecture Overview”
Section 14.2, “Configuration of Internal Memory Space”
Section 14.3, “Descriptor Overview”
Section 14.4, “Execution Units”
Section 14.5, “Channel”
Section 14.6, “Controller”
DEU—Data encryption standard execution unit
— DES, 3DES
— Two key (K1, K2, K1) or three key (K1, K2, K3)
— ECB and CBC modes for both DES and 3DES
AESU—Advanced encryption standard execution unit
— Implements the Rinjdael symmetric key cipher
— ECB, CBC, CCM, and counter modes
— 128-, 192-, 256-bit key lengths
MDEU—Message digest execution unit
— SHA with 160-, 224-, or 256-bit message digest
— MD5 with 128-bit message digest
— HMAC with either algorithm
One channel, supporting a queue of commands (descriptor pointers)
— Dynamic assignment of execution units through an integrated controller
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
The MPC8313 does not support a security engine.
NOTE
14-1

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