MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 837

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 15-120
15.5.3.10.11 Timer Offset Register (TMROFF_H/L)
The timer offset register is used to provide current time by adding its value to the clock counter. Figure
15-113 describes the definition of the TMROFF_H/L register.
Table 15-121
15.5.3.10.12 Alarm Time Comparator Register (TMR_ALARM1–2_H/L)
Alarm time comparator register (TMR_ALARMn_H/L). This register holds alarm time for comparison
with the current time counter. There are two of these registers for eTSEC1 which are shared amongst all
eTSECs. Figure 15-114 describes the definition for the TMR_ALARMn_H/L register.
Freescale Semiconductor
Offset eTSEC1:0x2_4E30 (H); 0x2_4E34 (L)
Reset
16–31
0–15
Bits
0–63
Bits
W
R
Offset eTSEC1:0x2_4E28
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0
W
R
PRSC_OCK Output clock division/prescale factor. Output clock is generated by dividing the timer input clock by this
TMROFF_H/L Offset value of the clock counter. Current time in is calculated by adding TMROFF_H/L with the
0
Name
—
describes the fields of the TMR_PRSC register.
describes the fields of the TMROFF_H/L register.
Name
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
All TMROFF_H registers in a device should be set to the same value, and
all TMROFF_L registers in a device should be set to the same value.
Otherwise, the precision time protocol may not work.
Reserved
number. Programmed value in this field must be greater than 1. Any value less than 1 is treated as 2.
timer’s counter TMR_CNT_H/L register.
TMROFF_H
Table 15-121. TMROFF_H/L Register Field Descriptions
Table 15-120. TMR_PRSC Register Field Descriptions
Figure 15-113. TMROFF_H/L Register Definition
Figure 15-112. TMR_PRSC Register Definition
—
NOTE
All zeros
31 32
15 16
Description
Description
Enhanced Three-Speed Ethernet Controllers
PRSC_OCK
TMROFF_L
Access: Read/Write
Access: Read/Write
31
15-119
63