MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1209

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Index
Q
Quality of service (QoS), see eTSEC
Queue element transfer descriptor (qTD), see USB interface,
Queue heads, see USB interface, queue heads
R
Real time clock module (RTC), 5-35
Recoverable exception, 7-18
Registers
Freescale Semiconductor
block diagram, 5-36, 5-41
external signals description, 5-36
features, 5-36
functional description, 5-41
initialization/application information
memory map/register definition, 5-37
modes of operation, 5-36
operational modes, 5-41
overview, 5-35
registers, 5-37–5-40
AFEU
by acronym, see Register Index
clock
configuration registers
crypto-channel
CSB arbiter and bus monitor, 6-2–6-10
DDR
DEU
DMA/messaging unit, 12-3–12-15
DUART, 18-5–18-18
eTSEC, 15-22–15-134
queue element transfer descriptor (qTD)
RTC programming guidelines, 5-42
status, 14-34, 14-44
configuration, 4-37–4-41
hardware implementation registers (HIDn)
configuration, 14-55
general, 14-55
configuration registers, 9-9–9-29
interrupt control, 14-25, 14-47
interrupt status, 14-24, 14-45
IV, 14-27
key, 14-28
key size, 14-20, 14-21, 14-42
mode, 14-19, 14-40
reset control, 14-22, 14-43
configuration, control, and status registers, 12-3–12-9
DMA attribute registers, 15-108
general control and status registers, 15-22
hash function registers, 15-106–15-108
lossless flow control registers, 15-109–15-110
PLL configuration, 7-23
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
Reset
EU assignment status, 14-67
fetch, 14-62
GPIO, 21-3–21-5
I/O sequencer, 11-3–11-6
I
ID, 14-73
interrupt
IPIC, 8-7–8-28
JTAG
JTAG interface, 20-3
LBC, 10-9
master control, 14-74
MDEU
PCI, 13-12–13-40
PKEU
reset
SPI, 19-9–19-16
time base facility (TBL/TBU)
USB interface
actions, 4-5
causes, 4-5
configuration, 4-9
2
C interface, 17-5
MAC registers, 15-67–15-79
MIB registers, 15-79–15-106
receive control and status registers, 15-48–15-63
ten-bit interface registers, 15-123–15-134
transmit control and status registers, 15-35–15-46
clear, 14-71
mask, 14-68
status, 14-70
boundary-scan registers, 20-3
bypass register, 20-3
instruction register, 20-3
status register, 20-3
context registers, 14-38
data size, 14-32, 14-37
interrupt control, 14-36
interrupt status, 14-32, 14-35
key, 14-39
key size, 14-32
mode, 14-28
reset control, 14-33
configuration access, 13-12–13-15
configuration space, 13-25–13-40
control and status, 13-15–13-25
EU_GO, 14-27, 14-38
status, 14-23
configuration, 4-13, 4-32–4-37
for reading, 7-17
capability registers, 16-7
operational registers, 16-11
Index-11
Q–R