MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 590

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
13-8
PCI_IRDY
PCI_INTA
PCI_PAR
Signal
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 13-3. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O PCI initiator ready. This signal is driven by the PCI controller when it is the initiator of a PCI transfer.
I/O PCI parity.
O
O
O
I
I
PCI interrupt A.
Outputs for the bi-directional initiator ready.
Inputs for the bi-directional initiator ready.
Outputs for the bi-directional parity.
Inputs for the bi-directional parity.
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
State
State
State
State
State
Asserted—The PCI controller signals an interrupt to the PCI host.
Negated—The PCI controller is not currently signalling an interrupt.
Asserted—The PCI controller, acting as a PCI master, can complete the current data
Negated—The PCI target needs to wait before this PCI controller, acting as a PCI master,
Asserted—Another PCI master can complete the current data phase of a transaction.
Negated—If PCI_FRAME is asserted, indicates a wait cycle from another master. If
Asserted—Odd parity across PCI_AD[31:0] and PCI_CBE[3:0] during address and data
Negated—Even parity across PCI_AD[31:0] and PCI_AD[31:0] during address and data
Asserted—Odd parity driven by another PCI master or the PCI target during address and
Negated—Even parity driven by another PCI master or the PCI target during address and
phase of a PCI transaction. During a write, this PCI controller asserts PCI_IRDY to
indicate that valid data is present on PCI_AD[31:0]. During a read, this PCI controller
asserts PCI_IRDY to indicate that it is prepared to accept data.
can complete the current data phase. During a write, this PCI controller negates
PCI_IRDY to insert a wait cycle when it cannot provide valid data to the target.
During a read, this PCI controller negates PCI_IRDY to insert a wait cycle when it
cannot accept data from the target.
PCI_FRAME is negated, indicates that the PCI bus is idle.
phases.
phases.
data phases.
data phases.
Description
Freescale Semiconductor