MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1087

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Additionally, the following three I
17.2
The following sections give an overview of signals and provide detailed signal descriptions.
17.2.1
The I
the signal patterns driven on SDAn represent address, data, or read/write information at different stages of
the protocol.
17.2.2
SDAn and SCLn, described in
devices connected to these signals must have open-drain or open-collector outputs. The logic AND
function is performed on both of these signals with external pull-up resistors. Refer to the hardware
specifications for electrical characteristics.
Freescale Semiconductor
Signal Name Idle State I/O
Serial Clock
Serial Data
(SDA1,
(SCL1,
SDA2)
SCL2)
•
•
•
2
C interface uses the SDAn and SCLn signals, described in
START condition. This condition denotes the beginning of a new data transfer (each data transfer
contains several bytes of data) and awakens all slaves.
Repeated START condition. A START condition that is generated without a STOP condition to
terminate the previous transfer.
STOP condition. The master can terminate the transfer by generating a STOP condition to free the
bus.
External Signal Descriptions
Signal Overview
Detailed Signal Descriptions
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
High
High
O As a master, the I
O When writing as a master or slave, the I
I
I
When the I
to synchronize incoming data on SDA n . The bus is assumed to be busy when SCL n is detected
low.
I
When the I
receives data from other
detected low.
2
C module drives SCL n negates for data pacing.
Table
Table 17-1. I
2
C–specific states are defined for the I
2
2
C module is idle or acts as a slave, SCL n defaults as an input. The unit uses SCL n
C module is idle or in a receiving mode, SDA n defaults as an input. The unit
17-2, serve as a communication interconnect with other devices. All
2
C module drives SCL n along with SDA n when transmitting. As a slave, the
2
C Interface Signal Descriptions
I
2
C
devices on SDA n . The bus is assumed to be busy when SDA n is
State Meaning
2
C module drives data on SDA n synchronous to SCL n .
Table
17-1, for data transfer. Note that
2
C interface:
I
2
C Interfaces
17-3