MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1185

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

14.5.1.2, 14-63
14.5.2.1, 14-65
15.2, 15-2
15.5.2, 15-12
15.5.3.1.1, 15-21
15.5.3.1.1, 15-22
15.5.3.1.3, 15-24
15.5.3.1.6, 15-30
15.5.3.1.6, 15-31
15.5.3.1.6, 15-32
15.5.3.1.8, 15-34
15.5.3.3.2, 15-40
15.5.3.3.3, 15-42
15.5.3.3.8, 15-46
15.5.3.4.1, 15-50
15.5.3.4.1, 15-50
15.5.3.4.1, 15-50
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 14-36 changed the title of the table to read: ‘Crypto-Channel Pointer Status
Register PAIR_PTR Field Values.’
Replaced ‘channel configuration register NT ad CDIE bits in the CCR,’ with
‘crypto-channel configuration register NT and CDIE bits in the CCCR.’
Added ‘and RTBI’ to physical interface sub-bullet, ‘1000 Mbps full-duplex
RGMII and RTBI.’
Removed register sections (and memory map rows) from MPC8313 product
which only have a 32-bit address space.
In Figure 15-2, corrected value of TSEC_ID[TSEC_REV_MN] to be 00.
In Table 15-5, corrected value of TSEC_ID[TSEC_REV_MN] to be 00.
Updated register to show that they are w1c (all fields).
Updated cross-references.
In Table 15-10, changed bit 16 to ‘Reserved’ and removed the rest of the text.
In Table 15-11, changed TBIM, SGMII fields from 0 to 1.
In Table 15-13, changed the description of DMACTRL[GTS] to the following:
If this bit is set, the Ethernet controller stops transmission after all frames that are
currently in the Tx FIFO or scheduled have been transmitted, and the GTSC
interrupt in the IEVENT register is asserted. A frame that has started reading
buffer descriptors or data from memory will be read to completion and be
transmitted before the GTSC interrupt occurs. However, if no frame has been
scheduled for transmission and the Tx FIFO is empty, the GTSC interrupt is
asserted immediately. once transmission has completed, clearing GTS will restart
transmit.
Updated register to show that they are w1c (all fields).
In Table 15-21, add the following note to DFVLAN[TAG]:
Note that, if using DFVLAN to set a custom ethertype (that is, using a value other
than 0x8100), packets received with a custom tag are not counted by any of the
RMON counters. Affected counters include TRMGV, RMCA, RBCA, RXCF,
RXPF, RXUO, RALN, RFLR, ROVR, RJBR, TMCA, TBCA, TXPF, TXCF.
Removed register sections (and memory map rows) from MPC8313 product
which only have a 32-bit address space.
In Table 15-32, add the following note to RCTRL[VLEX] and RCTRL[PRSDEP]:
If PRSDEP is cleared, VLEX must be cleared as well. (VLAN tag extraction is
only supported when the parser is enabled.)
In Table 15-32, add the following note to RCTRL[FILREN] and
RCTRL[PRSDEP]:
If PRSDEP is cleared, FILREN must be cleared as well.
Changed first sentence of RCTRL[PRSDEP] setting 00 to;
Revision History
A-27