MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 843

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5.4.3.2
Figure 15-118
Table 15-127
Freescale Semiconductor
10–15
Offset 0x01
Reset 0
Bits
Bits
0–6
10
11
9
7
8
9
W
R
0
Speed[1] Speed selection. This bit defaults to a set state and should always be set, which corresponds to 1000 Mbps
Remote
Extend
Status
Name
Name
Done
Fault
0
Pre
AN
No
—
—
—
0
describes the fields of the SR register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
describes the definition for the SR register.
Status Register (SR)
—
0
Reserved, should be cleared.
This bit indicates that PHY status information is also contained in the Register 15, Extended Status Register.
Returns 1 on read. This bit is read-only.
Reserved, should be cleared.
MF preamble suppression enable. This bit indicates whether or not the PHY is capable of handling MII
management frames without the 32-bit preamble field. Returns 1, indicating support for suppressed
preamble MII management frames. This bit is read-only.
Auto-negotiation complete. This bit is read-only and is cleared by default.
0 Either the auto-negotiation process is underway or the auto-negotiation function is disabled.
1 The auto-negotiation process has completed.
Remote fault. This bit is read-only and is cleared by default. Each read of the status register clears this bit.
0 Normal operation.
1 A remote fault condition was detected. This bit latches high in order for software to detect the condition.
speed.Setting this field controls the speed at which the TBI operates. The following table provides the
appropriate encoding. Its default is bit[2] = ‘0’; bit[9] = ’1’.
Reserved
0
0
0
6
Table 15-126. CR Field Descriptions (continued)
Extend
Status
1
Figure 15-118. Status Register Definition
7
Reserved
Reserved
1000 Mbps
Reserved
Maximum Operating Speed
Table 15-127. SR Descriptions
—
0
8
No Pre
1
9
AN Done
10
0
Description
Description
Remote
Bit 2
Fault
11
0
1
0
1
0
Enhanced Three-Speed Ethernet Controllers
AN Ability
Bit 9
0
0
1
1
12
1
Status
Link
13
0
Access: Read only
—
14
0
Extend
Ability
15
15-125
1