MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1033

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.6.12.3.1 Split Transaction Scheduling Mechanisms for Isochronous
Full-speed isochronous transactions are managed through a transaction translator's periodic pipeline. As
with full- and low-speed interrupt, system software manages each transaction translator's periodic pipeline
by budgeting and scheduling exactly during which micro-frames the start-splits and complete-splits for
each full-speed isochronous endpoint occur. The requirements described in Section Split Transaction
Scheduling Mechanisms for Interrupt apply.
conditions that are supported by the EHCI periodic schedule. The S
where software can schedule start- and complete-splits (respectively). The H-Frame boundaries are
marked with a large, solid bold vertical line. The B-Frame boundaries are marked with a large, bold,
dashed line. The bottom of
Freescale Semiconductor
Periodic Schedule
Start & Complete
End of H-Frame
Frame Wrap at
Micro-Frame 0
HS/FS/LS Bus
Normal Case
Micro-Frame
Micro-Frame
in H-Frame,
Case 2a:
Case 2b:
Case 1:
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 16-57. Split Transaction, Isochronous Scheduling Boundary Conditions
B-Frame N–1
7
6
Figure 16-57
0
7
S
C
S
S
0
6
1
0
S
1
illustrates the relationship of an siTD to the H-Frame.
2
1
C
S
C
2
0
0
Figure 16-57
3
2
H-Frame N
C
C
S
3
1
1
siTD
4
3
B-Frame N
x
OUT
IN
C
S
C
S
2
0
2
illustrates the general scheduling boundary
5
4
C
C
S
3
1
3
n
6
5
C
S
C
and C
2
0
4
7
6
n
C
C
S
labels indicate micro-frames
1
3
5
IN
0
7
OUT
S
Universal Serial Bus Interface
IN
C
C
2
6
H-Frame N+1
siTD
1
0
C
3
B-Frame N+1
x+1
16-105