MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 621

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset 0x46
Reset
13.3.3.25 PCI Arbiter Control Register (PCIACR)
Figure 13-43
Table 13-41
Freescale Semiconductor
W
R
11–7
Bits
Bits
14
13
12
15
2
1
0
AD
cfg
15
shows the bit settings of the PCIACR.
PM
Table 13-40. PCI Function Configuration Register Field Descriptions (continued)
14
shows the PCI arbiter control register (PCIACR) fields.
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PBMD
Name
Name
MLTD
TLTD
PM
AD
HA
—
—
Table 13-41. PCI Arbiter Control Register (PCIACR) Field Descriptions
—
13
0
Arbiter disable. Indicates whether the PCI controller functions as the arbiter for the PCI bus. It
provides the value of the PCI arbiter enable configuration bit as sampled at the end of the reset
sequence.
configuration.
0 Arbiter enabled
1 Arbiter disabled
Parking mode. Controls which device receives a bus grant when there are no outstanding bus
requests and the bus is idle.
0 The bus is parked with the last device to use the bus.
1 The bus is parked with the PCI controller.
Reserved
PCI broken master disable. Determines whether the PCI controller ignores the bus requests of an
initiator that requests the bus for an excessive period without using it.
0 An initiator that requests the bus and receives the grant must begin using the bus within 16 PCI
1 No requests are ignored.
Reserved
Target latency timeout disable. Determines whether the PCI controller, while acting as a PCI target,
times out when the first data phase of a transaction has not completed in 16 PCI cycles.
0 Target latency timeout enabled.
1 Target latency timeout disabled.
Master latency timer disable. Determines whether the PCI controller, while acting as a PCI master,
terminates a transaction upon the expiration of the master latency timer.
0 Master latency timer enabled.
1 Master latency timer disabled.
Host/Agent. Indicates whether the PCI controller is in host mode or agent mode. It provides the
value of the PCI_HOST—PCI host configuration bit is sampled at the end of the reset sequence.
0 Host mode
1 Agent mode
PMBD
clock periods after the bus becomes idle or its request is subsequently ignored.
12
0
Figure 13-43. PCI Arbiter Control Register (PCIACR)
11
0
SeeChapter 4, “Reset, Clocking, and Initialization,”
0
—
0
0
0
7
Description
Description
PRI0
0
6
PRI1
0
5
for more information on reset
PRI2
0
4
3
0
Access: Read/Write
—
0
PCI Bus Interface
0
1
13-39
MPRI
0
0