MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 522

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.4.4.1.1
The user must ensure that the UPM is appropriately initialized before a request occurs.
The UPM supports two types of memory reads and writes:
The user must ensure that patterns for single-beat transfers contain one, and only one, transfer
acknowledge (UTA bit in RAM word set high) and for a burst transfer, contain the exact number of transfer
acknowledges required.
Any transfers that do not naturally fit single or burst transfers are synthesized as a series of single transfers.
These accesses are treated by the UPM as back-to-back, single-beat transfers. Burst transfers can also be
inhibited by setting OR
32-byte aligned with a transaction size being some multiple of 32-bytes, which is a natural fit for
cache-line transfers, for example.
10.4.4.1.2
Each UPM contains a refresh timer that can be programmed to generate refresh service requests of a
particular pattern in the RAM array.
memory refresh timer request generation. The UPM refresh timer register (LURT) defines the period for
the timers associated with all three UPMs.
By default, all local bus refreshes are performed using the refresh pattern of UPMA. This means that if
refresh is required, MAMR[RFEN] must be set. It also means that only one refresh routine should be
programmed and be placed in UPMA, which serves as the refresh executor. Any banks assigned to a UPM
are provided with the common UPMA refresh pattern if the RFEN bit of the corresponding UPM is set,
concurrently. UPMA assigned banks, therefore, always receive refresh services when MAMR[RFEN] is
set, while UPMB and UPMC assigned banks also receive (the same) refresh services if the corresponding
MxMR[RFEN] bits are set. In this scenario, more than one chip select may assert at the same time, as
refresh pattern runs for all banks assigned to UPM with RFEN bit set.
10-74
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A single-beat transfer transfers one operand consisting of up to a single word (dependent on port
size). A single-beat cycle starts with one transfer start and ends with one transfer acknowledge.
A burst transfer transfers exactly 4 double words regardless of port size. For 32-bit accesses, the
burst cycle starts with one transfer start but ends after eight transfer acknowledges, whereas an
8-bit device requires 32 transfer acknowledges.
System
Clock
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Memory Access Requests
UPM Refresh Timer Requests
Figure 10-60. Memory Refresh Timer Request Block Diagram
n
[BI]. Burst performance can be achieved by ensuring that UPM transactions are
Table 10-39. UPM Routines Start Addresses (continued)
Refresh timer (RTS)
Exception condition (EXS)
PTP Prescaling
UPM Routine
Figure 10-60
shows the clock division hardware associated with
Divide by LURT
Routine Start Address
0x3C
0x30
UPM refresh timer request
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